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data sheet rev. 2.2 / april 2012 asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic ? 2012 zentrum mikroelektronik dresden ag? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. brief description asi4u is a new generation cmos integrated circuit for as-i networks. the low-level field bus as-i (actuator sensor interface) was designed for easy, safe and cost- effective interconnection of sensors, actuators and switches. it transports both power and data over the same two-wire unshielded cable. asi4u is used as a part of a master or slave node and works as an interface to the physical bus. the device realizes power supply, physical data transfer and communication protocol handling. asi4u is fully compliant with as-i complete specification 3.0 and functioning and pin compatible with the a2si ic. all configuration data are stored in an internal eeprom that can be easily programmed by a stationary or handheld programming device. the special as-i safety option assures short response times regarding security related events. features ? compliant with as-i complete specification v3.0 ? universal application: in slaves, masters, repeaters and bus-monitors ? compatible with a2si ? floating as-i transmitter and receiver for high symmetrical high power applications ? on-chip electronic inductor with current drive capability of 55 ma ? two configurable led outputs to support all spec. v3.0 status indication modes ? several data pre-processing functions, including configurable data input filters and bit selective data inverting ? additional addressing channel for easy wireless module setup ? support of 8 / 16 mhz crystals by automatic frequency detection ? special as-i safety option ? clock watchdog for high system security benefits ? flexible, separated i/os ? flexible as-i bus adoption (isolated transceiver) ? very small package ssop 28 (asi4u) ? supports as-i complete specification v3.0 ? supports high ambient temperature applications (asi4u-e) available support ? zmdi as-interface programmer kit usb ? zmdi asi4u evaluation board v2.0 physical characteristics ? operational temp. range: -25 to +85c (asi4u) ? operational temp. range: -40 to +85c (asi4u-f) ? operational temp. range: -25 to +105c (asi4u-e) ? ssop28 (asi4u) / sop28 (asi4u-e) package asi4u basic application circuit +24v +0v asi+ asi- +24v +0v asi+ asi- asi4u gnd 0v u5r cap asin asip osc2 osc1 uin uout fid di0...3 do0...3 dsr p0...3 ird led2 led1 pst asi4u gnd 0v u5r cap asin asip osc2 osc1 uin uout fid di0...3 do0...3 dsr p0...3 ird led2 led1 pst standard application extended power application with ir-addressing option
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic typical applications ? as-i master modules ? as-i slave modules ? as-i safety modules asi4u block diagram ordering information ordering code type operating temperature range package type rohs conform packaging minumum order quantity asi4ue-g1-st standard -25c to +85c ssop28 / 5.3mm y tube (47 parts/tube) 470 pcs. (10 tubes) asi4ue-g1-sr standard -25c to +85c ssop28 / 5.3mm y tape & reel (1500 parts/reel) 1500 pcs. (one reel) asi4ue-g1-sr-7 standard -25c to +85c ssop28 / 5.3mm y tape & reel (500 parts/reel) 500 pcs. (one 7" reel) asi4ue-g1-mt master -25c to +85c ssop28 / 5.3mm y tube (47 parts/tube) 470 pcs. (10 tubes) asi4ue-g1-mr master -25c to +85c ssop28 / 5.3mm y tape & reel (1500 parts/reel) 1500 pcs. (one reel) asi4ue-e-g1-st standard -25c to +105c sop28 / 300 mil y tube (27 parts/tube) 270 pcs. (10 tubes) asi4ue-e-g1-sr standard -25c to +105c sop28 / 300 mil y tape & reel (1000 parts/reel) 1000 pcs. (one reel) asi4ue-f-g1-st standard -40c to +85c ssop28 / 5.3mm y tube (47 parts/tube) 470 pcs. (10 tubes) ASI4UE-F-G1-SR standard -40c to +85c ssop28 / 5.3mm y tape & reel (1500 parts/reel) 1500 pcs. (one reel) sales and further information www.zmdi.com asi@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95035-7453 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, korean office posco centre building west tower, 11th floor 892 daechi, 4-dong, kangnam-gu seoul, 135-777 korea phone +49.351.8822.7274 fax +49.351.8822.87274 phone +855-ask-zmdi (+855.275.9634) phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.2377.8189 fax +886.2.2377.8199 phone +82.2.559.0660 fax +82.2.559.0700 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished he reby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for any special, indirect, incident al, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby expressly dis claims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), strict liability, or otherwise.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 4 of 63 contents 0 read this first ................................................................................................................ ........................... 6 0.1. important notice............................................................................................................... ................... 6 0.2. asi-safety applications........................................................................................................ ............... 6 0.3. repair of asi-safety modules ................................................................................................... .......... 6 1 general device specification................................................................................................... .................. 6 1.1. absolute maximum ratings (non operating) ...................................................................................... 6 1.2. operating conditions ........................................................................................................... ............... 6 1.3. quality standards .............................................................................................................. ................. 6 1.4. package pin assignment ......................................................................................................... ........... 6 2 basic functional description....................... ............................................................................ ................... 6 2.1. functional block diagram ....................................................................................................... ............ 6 2.2. general operational modes ...................................................................................................... .......... 6 2.3. slave mode ..................................................................................................................... .................... 6 2.3.1. as-i communication channel ..................................................................................................... ... 6 2.3.2. ird communication channel ...................................................................................................... ... 6 2.3.3. parameter port pins ............................................................................................................ ......... 6 2.3.4. data port pins ................................................................................................................. ............. 6 2.3.5. data input inversion........................................................................................................... ........... 6 2.3.6. data input filtering ........................................................................................................... ............ 6 2.3.7. fixed data output driving ...................................................................................................... ...... 6 2.3.8. synchronous data i/o mode ...................................................................................................... .. 6 2.3.9. 4 input / 4 output processing in extended address mode ............................................................ 6 2.3.10. as-i safety mode............................................................................................................... ........... 6 2.3.11. enhanced led status indication ................................................................................................. .6 2.3.12. communication monitor/watchdog............................................................................................... 6 2.3.13. write protection of id_code_extension_1 .................................................................................... 6 2.3.14. summary of master calls ........................................................................................................ ..... 6 2.4. master mode .................................................................................................................... ................... 6 2.5. e2prom ......................................................................................................................... .................... 6 3 detailed functional description ................................................................................................ ................. 6 3.1. as-i receiver .................................................................................................................. .................... 6 3.2. as-i transmitter ............................................................................................................... ................... 6 3.3. addressing channel input ird................................................................................................... ......... 6 3.3.1. general slave mode functionality ............... ................................................................................ .6 3.3.2. ac current input mode.......................................................................................................... ....... 6 3.3.3. cmos input mode................................................................................................................ ........ 6 3.3.4. master-, repeater- and monitor-mode.......................................................................................... 6 3.4. digital inputs - dc characteristics ............................................................................................ .......... 6 3.5. digital outputs - dc characteristics........................................................................................... ......... 6
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 5 of 63 3.6. parameter port and pst pin..................................................................................................... .......... 6 3.6.1. slave mode..................................................................................................................... .............. 6 3.6.2. parameter multiplex mode....................................................................................................... ..... 6 3.6.3. special function of p0, p1 and p2 .............................................................................................. .. 6 3.6.4. master-, repeater-, monitor mode............................................................................................... .6 3.7. data port and dsr pin .......................................................................................................... ............. 6 3.7.1. slave mode..................................................................................................................... .............. 6 3.7.2. input data pre-processing...................................................................................................... ...... 6 3.7.3. fixed output data driving ...................................................................................................... ...... 6 3.7.4. synchronous data i/o mode ...................................................................................................... .. 6 3.7.5. support of 4i/4o processing in extended addr ess mode, profile 7.a.x.e ..................................... 6 3.7.6. safety mode operation.......................................................................................................... ....... 6 3.7.7. master-, repeater-, monitor mode............................................................................................... .6 3.7.8. special function of dsr........................................................................................................ ........ 6 3.8. fault indication input pin fid................................................................................................. ............. 6 3.8.1. slave mode..................................................................................................................... .............. 6 3.8.2. master- and monitor mode....................................................................................................... ..... 6 3.9. led outputs .................................................................................................................... .................... 6 3.9.1. slave mode..................................................................................................................... .............. 6 3.9.2. communication via addressing channel ...................................................................................... 6 3.9.3. master-, repeater-, monitor mode............................................................................................... .6 3.10. oscillator pins osc1, osc2..................................................................................................... .......... 6 3.11. ic reset....................................................................................................................... ....................... 6 3.11.1. power on reset ................................................................................................................. .......... 6 3.11.2. logic controlled reset ......................................................................................................... ......... 6 3.11.3. external reset ................................................................................................................. ............. 6 3.12. uart ........................................................................................................................... ....................... 6 3.12.1. as- i input channel ............................................................................................................ ........... 6 3.12.2. addressing channel ............................................................................................................. ........ 6 3.13. main state machine ............................................................................................................. ............... 6 3.14. communication monitor/watchdog ................................................................................................. .... 6 3.15. toggle watchdog for 4i/4o processing in ex tended address mode .................................................... 6 3.16. write protection of id_code_extension_1 ........................................................................................ .. 6 3.17. power supply................................................................................................................... ................... 6 3.17.1. voltage output pins uout and u5r............................................................................................ 6 3.17.2. input impedance (as-i bus load) ................................................................................................ .. 6 3.18. thermal and overload protection ................................................................................................ ....... 6 4 application circuits ........................................................................................................... ......................... 6 5 package outline (sop28 / asi4u-e).............................................................................................. ........... 6 6 package outline (ssop28 / asi4u / asi4u- f) ..................................................................................... .... 6
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 6 of 63 7 package marking................................................................................................................ ....................... 6 8 ordering information........................................................................................................... ....................... 6 9 related documents ............. ................................................................................................. ..................... 6 10 related products ............................................................................................................... ........................ 6
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 7 of 63 list of figures figure 1: ptot = f( ? a ).............................................................................................................................. .................. 6 figure 2: asi4u package pin assignment......................................................................................... ..................... 6 figure 3 functional block diagram .............................................................................................. ........................... 6 figure 7: receiver comparator threshold set-up in principle .................................................................... ............... 6 figure 8: addressing channel input (ird), phot o-current waveforms.............................................................. ...... 6 figure 9: timing diagram parameter port p0 ... p3, pst ......................................................................... .............. 6 figure 10: timing diagram data port do0 ... do3, di0 ? di3, dsr................................................................ ....... 6 figure 12: principle of input filtering........................................................................................ ................................ 6 figure 13: principle of as-i cycle input filtering (exe mplary for slave with address 1) ........................................ .... 6 figure 14: flowchart - input d3 (d2,d1) in safety mode ......................................................................... ............... 6 figure 15: flowchart - input d0 in safety mode................................................................................. ..................... 6 figure 16: flowchart - data_exchange_disable ................................................................................... .................. 6 figure 17: power-on behavior (all modes) ....................................................................................... ...................... 6 figure 18: timing diagram external reset via dsr ............................................................................... ................. 6 figure 19: manchester-ii-modulation princi ple .................................................................................. ...................... 6 figure 20: standard application circuit with bi-directional data i/o ........................................................... .............. 6 figure 21: extended power application circuit.................................................................................. ....................... 6 figure 22: asi4u master mode application ....................................................................................... ..................... 6 figure 23: sop package ......................................................................................................... ............................... 6 figure 24: package dimensions .................................................................................................. ........................... 6 figure 25: ssop package........................................................................................................ .............................. 6 figure 26: package outline dimensions .......................................................................................... ....................... 6 figure 27: package marking ..................................................................................................... .............................. 6
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 8 of 63 list of tables table 1: absolute maximum ratings .............................................................................................. ........................ 6 table 2: operating conditions .................................................................................................. .............................. 6 table 3: crystal frequency..................................................................................................... ................................ 6 table 4: asi4u pin list........................................................................................................ ................................... 6 table 5: assignment of operational modes ....................................................................................... ...................... 6 table 6: asi4u master calls and related slave responses ........................................................................ .......... 6 table 7: e2prom content ........................................................................................................ .............................. 6 table 8: receiver parameters ................................................................................................... ............................. 6 table 9: transmitter current amplitude ......................................................................................... ......................... 6 table 10: ird ac current input parameters ...................................................................................... ...................... 6 table 11: ird current/voltage mode switching................................................................................... ..................... 6 table 12: ird cmos input levels................................................................................................ .......................... 6 table 13: polarity of manchester-ii-signal at ird in master mode............................................................... ........... 6 table 14: dc characteristics of digital high voltage input pins................................................................ ................ 6 table 15: dc characteristics of digital high voltage output pins ............................................................... .............. 6 table 16: timing parameter port ................................................................................................ ............................ 6 table 17: parameter port output signals in master -, repeater-, monitor-mode .................................................... .. 6 table 18: timing data port outputs............................................................................................. ........................... 6 table 19: data input filter time constants..................................................................................... ........................ 6 table 20: input filter activation by paramete r port pin p1 ..................................................................... ................ 6 table 21: e2prom configuration for different input modes....................................................................... .............. 6 table 22: activation states of synchronous data io mode ........................................................................ ............. 6 table 23: meaning of master call bits i0 ? i3 in ext_addr_4i/4o_mode ........................................................... ..... 6 table 24: control signal inputs in master-, repeater- and monitor mode ......................................................... ...... 6 table 25: error signal outputs in monitor mode ................................................................................. ..................... 6 table 26: power fail detection at fid (master mode and monitor mode)........................................................... .... 6 table 27: led status indication ................................................................................................ .............................. 6 table 28: polarity of manchester-ii-signal at led1 ............................................................................. ................... 6 table 29: oscillator pin parameters ............................................................................................ ............................ 6 table 30: ic initialization times .............................................................................................. ................................. 6 table 31: power on reset threshold voltages .................................................................................... .................. 6 table 32: timing of external reset............................................................................................. .............................. 6 table 33: properties of voltage output pins uout and u5r....................................................................... ............ 6 table 34: as-i bus load properties............................................................................................. ........................... 6 table 35: cap pin parameters................................................................................................... ............................. 6 table 36: shutdown temperature................................................................................................. .......................... 6 table 37: package dimensions (mm) .............................................................................................. ....................... 6 table 38: package dimensions (mm) .............................................................................................. ....................... 6
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 9 of 63 0 read this first 0.1. important notice products sold by zentrum mikroelektronik dresden ag (zmdi) are covered exclusively by the warranty, patent indemnification and other provisions appearing in zmdi standard "terms of sale". zmdi makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the materials pertaining to zmdi products, or regarding the freedom of any products described in the materials from patent and/or other infringement. zmdi reserves the right to discontinue production and change specifications and prices of its products at any time and without notice. zmdi products are intended for use in commercial applications. applications requiring extended temperatur e range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional mutually agreed upon processing by zmdi for such applications. zmdi reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 0.2. asi-safety applications the asi4u is designed to allow replacement of a2si ics in existing board layouts and applications. however, since the asi4u provides additional data preprocessing functions at the data input channel, the fault reaction time of an as-i safety module could increase by 40ms if some of the new features become activated by intention, by accident or hardware fault. zmdi strongly recommends the use of the new asi4u safety-mode, if the asi4u shall replace the a2si in existing asi-safety designs. only then, the same fault reaction times as with the a2si are guaranteed. for compatibility with the modified data input routing in safety mode, the user has to adapt the safety code table stored in the external micro controller. only such safety code sequences that contain the value 1110 are permitted. if the ic is operated in safety mode, the user must pay special attention that the synchronous data i/o mode as well as the data input filters remain disabled by appropriate e2prom configuration. application of the asi4u in standard mode (no safety mode enabled) for as-i safety products is basically possible, if an additional fault reaction time of 40ms is taken into account. the user shall also obey the additional security advice regarding ?production and repair of as-i safety slaves? that is available as an additional document form the zmdi web page www.zmdi.com . 0.3. repair of asi-safety modules if an a2si based asi-safety module shall be repaired, it is explicitly prohibited to replace the a2si ic with the newer asi4u ic. this is to exclude safety relevant deviations of module properties that can result from the different data input paths and the above mentioned possible increase in fault reaction time. the user shall also obey the additional security advice regarding ?production and repair of as-i safety slaves? that is available as an additional document form the zmdi web page www.zmdi.com . safety-advice
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 10 of 63 1 general device specification 1.1. absolute maximum ratings (non operating) table 1: absolute maximum ratings symbol parameter min max unit note v 0v , v gnd voltage reference 0 0 v v asip-asin voltage difference between asip and asin (v asip - v asin ) -0.3 40 v 1 v asip-asin_p pulse voltage between asip and asin (v asip - v asin ) -0.3 50 v 2 v asip pulse voltage between asip and 0v (v asip ? v 0v ) -0.3 50 v 2, 3 v asin voltage between asin and 0v (v asin ? v 0v ) -6.0 6.0 v 3 v uin power supply input voltage -0.3 40 v v uin_p pulse voltage at power supply input -0.3 50 v 2 v inputs1 voltage at pins di3 ... di0, do 3 ... do0, p3 ... p0, dsr, pst, led1, led2, fid, ird, uout -0.3 v uout + 0.3 v v inputs2 voltage at pins osc1, osc2, cap, u5r -0.3 7 v i in input current into any pin except supply pins -50 50 ma 4 h humidity non-condensing 5 v hbm1 electrostatic discharge ? human body model (hbm1) 3500 v 6 v hbm2 electrostatic discharge ? human body model (hbm2) 2000 v 7 v edm electrostatic discharge ? equipment discharge model (edm) 400 v 8 ? stg storage temperature -55 125 c p tot total power dissipation 0.85 w 9 r thj thermal resistance of ssop 28 package thermal resistance of sop 28 package 40 60 80 80 k/w 10 1 reverse polarity protection has to be performed externally 2 pulse with ? 50s, repetition rate ? 0.5 hz 3 v asip-asin and v asip-asin_p must not be violated 4 latch-up resistance, reference pin is 0v 5 level 3 according to jedec-020d is guaranteed 6 hbm1: c = 100pf charged to v hbm1 with resistor r = 1.5k ? in series, valid for asip-asin only. 7 hbm2: c = 100pf charged to v hbm2 with resistor r = 1.5k ? in series, valid for all pins except asip- asin 8 edm: c = 200pf charged to v edm with no resistor in series, valid for asip-asin only 9 at max. operating temperature, the allowed total power dissipation depends on additional thermal resistance from package to ambient and on the operation ambient temperature as shown in figure 1. 10 single layer board, p tot = 0.5w; air velocity = 0m/s ? max. value; air velocity = 2.5m/s ? min. value p tot = f (ta); 1l / 2l = 1 layer / 2 layer pcb 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 -25 0 25 50 75 100 ta ptot (2l) ptot (1l) figure 1: ptot = f( ? a )
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 11 of 63 1.2. operating conditions table 2: operating conditions symbol parameter min max. unit note v uin positive supply voltage for ic operation 16 33.1 v 1 v 0v , v gnd negative supply voltage 0 0 v v asip dc voltage at asip relating to v 0v 16 33.1 v 2 v asin dc voltage at asin relating to v 0v -4 4 v 2 i uin operating current at v uin = 30v 6 ma 3 i cl1 max. output sink current at pins do3...do0, dsr 10 ma i cl2 max. output sink current at pins p0...p3, pst 10 ma ? amb ambient temperature range, operating range (asi4u) asi4u-e asi4u-f -25 -25 -40 85 105 85 c c c 1 dc-parameter: v uinmin = v uoutmin + v dropmax v uinmax = v uoutmax + v dropmin below v uinmin the power supply block may not be able to provide the specified output currents at uout and u5r. 2 outside of these limits the send current shape and send current amplitude cannot be guaranteed. 3 f c = 8.000 mhz, no load at any pin, transmitter tur ned off, digital state machine is in idle state table 3: crystal frequency symbol parameter nom. unit note f c crystal frequency 8.000/16.000 mhz 4 4 the ic automatically detects whether the crystal frequency is 8.000mhz or 16.000mhz and controls the internal clock circuit accordingly. the frequency detection is locked as soon as one as-i telegram was correctly received at any input channel . it can be reset by power on reset only. note: in slave mode the locking occurs if a master call was received. in master-/ repeater-/monitor mode a master call or a slave response that was received on any input channel, triggers the frequency locking. the asi4u supports an integrated clock watchdog. if no crystal or clock oscillation is recognized for 150s the ic generates a reset event until clock oscillation is available. more detailed oscillator pin definitions can be found in chapter 3.10 on page 6. 1.3. quality standards the quality of the ic will be ensured according to the zmdi quality standards. functional device parameters are valid for device operating conditions specified in chapter 1.2. production device tests are performed within the recommended ranges of v asip - v asin , v in - v 0v , ? amb = + 25c (+ 85c and - 25c/[-40c asi4u-f] on sample base only) unless otherwise stated.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 12 of 63 1.4. package pin assignment table 4: asi4u pin list package pin number name direction type description 1 asip in analog as-i transmitter/receiver input, to be connected to asi+ lead of as-i cable, via reverse polarity protection diode 2 asin out analog as-i transmitter/receiver output, to be connected to asi- lead of as-i cable 3 0v supply ic ground common ground for all ic ports except asip/asin, to be connected to asin if no external coils are used 4 ird in analog / cmos (5v) addressing channel input 5 fid in pull-up periphery fault input 6 osc2 out analog (5v) crystal oscillator 7 osc1 in analog / cmos (5v) crystal oscillator / external clock input 8 do3 out open drain data port output d3 9 do2 out open drain data port output d2 10 do1 out open drain data port output d1 11 do0 out open drain data port output d0 12 gnd supply digital i/o ground, to be connected with 0v 13 p3 i/o pull-up/open drain parameter port p3 14 p2 i/o pull-up/open drain parameter port p2 / receive strobe output in master mode 15 p1 i/o pull-up/open drain parameter port p1 / power fail output in master mode 16 p0 i/o pull-up/open drain parameter port p0 / data clock output in master mode 17 di0 in pull-up data port input d0 18 di1 in pull-up data port input d1 19 di2 in pull-up data port input d2 20 di3 in pull-up data port input d3 21 pst i/o pull-up/open drain parameter strobe output (input function used for ic test purposes only) 22 dsr i/o pull-up/open drain data strobe output / reset input 23 led2 out open drain led output "enhanced diagnosis", to be activated by led2_active bit in the firmware region of the e2prom 24 led1 i/o pull-up/open drain led output "as-i-diagnosis" / addressing channel output (input function used for ic test purposes only) 25 cap i/o analog filter control (electronic inductor) 26 u5r out analog regulated internal/external 5v supply 27 uout out analog decoupled actuator/sensor supply 28 uin supply power supply input all open drain outputs are nmos based. pull-up properties at input stages are achieved by current sources referring to u5r.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 13 of 63 figure 2: asi4u package pin assignment asip asin 0v ird fid osc2 osc1 do3 do2 do1 do0 gnd p3 p2 uin uout u5r cap led1 led2 dsr pst di3 di2 di1 di0 p0 p1
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 14 of 63 2 basic functional description 2.1. functional block diagram figure 3 functional block diagram following device functions are associated with the different blocks of the ic: receive the receive block converts the analog telegram waveform from the as-i bus to a digital pulse coded signal that can be processed further by a digital uart circuit. the receive block is directly connected to t he as-i line pins asip and asin. it converts the differential as-i telegram to a single ended signal and removes the dc offset by high pass filtering. to adapt quickly on changing signal amplitudes in telegrams from different network users, the amplitude of the first telegram pulse is measured by a 3 bit flash adc and the threshold of a positive and a negativ e comparator is set accordingly to about 50% of the measured level. the comparators generate the p-pulse and n-pulse signals. transmit the transmit block transforms a digital response signal to a correctly shaped send current signal which is applied to the as-i bus. due to the inductive network behavior of the network the changing send current induces voltage pulses on the network line that overlay the dc operating voltage. the voltage pulses shall have sin2-wave shapes. hence, the send current shape must follow the integral of the sin2-wave function. receive transmit power supply oscillator digital logic thermal / overload protection asi4u a gnd lgnd di(3:0) dsr pst p(3:0) u in u out u5r osc1/2 cap asip asin over-heat p-pulse n-pulse rec-reset send-d send-sby power-on reset u out shut-down clk output stage input stage i/o stage output stage input stage output stage output stage input stage cmos input stage a c current input data-out data-in data-strb reset param strb param in param out led out fault_in a c electronic inductor u5rd pwr_fail logic ird_in a na dig over-load fid led2 led1 ird gnd 0v
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 15 of 63 digital logic the digital logic block contains uart, main state machine, e2prom memory and other control logic. e2prom write access and other i/o operations of the main state machine are supported in slave mode only (see description of general ic operational modes below). in master mode the ic is basically equivalent to a physical layer transceiver. if slave mode is activated, the uart demodulates the received telegrams, verifies telegram syntax and timing and controls a register interface to the main state machine. after reception of a correct telegram, the uart generates appropriate receive strobe signals that tell the main state machine to start further processing. the main state machine decodes the telegram information and starts respective i/o processes or e2prom access. a second register interface is used to send data back to the uart for construction of a telegram response. the uart modulates the response data into a manchester-ii-coded bit stream that is used to control the transmit unit. electronic inductor the electronic inductor is basically a gyrator circuit. it provides an inductive behavior between the ic pins uin and uout while the inductance is controlled by the capacitor on pin cap. the inductor shall decouple the power regulator of the ic as well as the external load circuit from the as-i bus and hence prevent cross talk or switching noise from disturbing the telegram communication on the bus. the as-i complete specification describes the input impedance behavior of a slave module by an equivalent circuit that consists of r, l and c in parallel. for example, a slave module in extended address mode shall have r > 13.5 kohm, l > 13.5 mh and c < 50pf. the electronic inductor of the asi4u delivers values that are well within the required ranges for output currents up to 55ma. more detailed parameters can be found in chapter 3.17.2. the electronic inductor requires an external capacitor of 10f at pin uout for stability. power supply the power supply block consists of a bandgap referenced 5v-regulator as well as other reverence voltage and bias current generators for internal use. the 5v regulator requires an external capacitor at pin u5r of at least 1f for stability. it can source up to 4ma for external use, however the power dissipation and the resulting device heating become a major concern, if too much current is drawn from the regulator. oscillator the oscillator supports direct connection of 8.000 mhz or 16.000 mhz crystals with a dedicated load capacity of 12pf and parasitic pin capacities of up to 8pf. the ic automatically detects the oscillation frequency of the connected crystal and controls the internal clock generator circuit accordingly. after power-on reset the ic is set to 16.0 00 mhz operation by default. after about 200s it will either switch to 8.000 mhz operation or remain in the 16.000 mhz mode. the frequency detection is active until the first as-i telegram was successfully received in order to make sure the ic found the correct clock frequency setting. the detection result is locked thereafter to increase resistance against burst or other interferences. the oscillator unit also contains a clo ck watch dog circuit that can generate an unconditioned ic reset if there was no clock oscillation for more than about 20s. this is to prevent the ic from unpredicted behavior if no clock signal is available anymore. thermal / overload protection the ic is self protected against thermal overheating and short circuiting of pin uout towards ic ground. if the silicon die temperature rises above around 140c for more than 2 seconds, the ic detects thermal overheating, switches off the electronic inductor, performs an ic reset and sets all analog blocks to power down mode. the 5v -regulator is of course also turned off in this state, however, there will still remain a voltage of about 3 ? 3.5v available at u5r that is derived from the internal start circuitry. the overheat protection state can only be left by power-cycling the as-i voltage. shortcutting pin uout towards ic ground leads to the same ic behavior as thermal overheating.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 16 of 63 ird cmos / ac current input the ird pin is input for the additional addressing channel in slave mode (see description of general ic operational modes below) or direct as-i transmitter input in master mode. in slave mode it can be operated either in cmos mode or ac-current input mode. the later is provided for direct connection of a photo diode. more detailed information can be found in chapter 3.3 addressing channel input ird. fid digital / analog stage pin fid can be set to digital cmos mode or analog voltage input mode. in slave mode it is set to cmos operation, in master mode it works in analog mode and acts as input for the power fail comparator. input stage all digital inputs, except of the oscillator pins, have high voltage capabilities and partly schmitt-trigger and pull-up features. for more details see chapter 3.4 digital inputs - dc characteristics . output stage all digital output stages, except of the oscilla tor pins, have high voltage capabilities and are implemented as nmos open drain buffers. each pin can sink up to 10ma of current. 2.2. general operational modes the asi4u provides two main and two additional sub operational modes. main operation modes divide in slave mode and master mode. sub operation modes divide in repeater mode and monitor mode. the later were derived from master mode in providing different output signals at the parameter port. a definition of which operational mode becomes active is made by programming the flags master_mode and repeater_mode in the firmware area of the e2prom (see also table 7 on page 6). the e2prom is read out at every initialization of the ic. online mode switchin g is not provided. the following configurations apply: table 5: assignment of operational modes selected operational mode master mode flag repeater mode flag slave mode 0 0 master mode 1 0 repeater mode 1 1 monitor mode 0 1 in slave mode the asi4u operates as fully featured as-i slave ic according to as-i complete specification v3.0. in master mode the asi4u translates a digital output sig nal from the master control logic (etc. plc, p, ?) to a correctly shaped, analog as-i pulse sequence and vice versa. every as-i telegram received is checked for consistency with the as-i communication protocol specif ications and if no errors were found, an appropriate receive strobe signal is generated. master mode and monitor mode differ in the kind of signaled telegrams. in master mode a single receive strobe signal is provided validating every correctly received slave response while in monitor mode two different receive strobe signals are available displaying every correctly received master and slave telegram separately. the monitor mode is inte nded for use in intelligent slaves and bus monitors that provide own telegram decoding mechanisms but do not check for correct telegram timing or syntax. the repeater mode is specifically provided for as-i bus repeater applications. 2.3. slave mode the slave mode is probably the most complex operational mode of the ic. the asi4u does not only support all mandatory as-i slave functions but also a variety of additional features that shall make as-i slave module design very easy and flexible.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 17 of 63 2.3.1. as-i communication channel in slave mode the asi4u can work on two different communication channels, the as-i channel and the ird channel. the as-i channel is directly connected to as-i bus via the pins asip and asin. a receiver and a transmitter unit are connected in parallel to the pins t hat allow fully bi-directional communication through asip and asin. the asi4u is the first ic that supports floating operation of the as-i receiver and transmitter (within certain limits) in relation to ic ground. thus far, the asin pin always had to be on the same potential like ic ground, preventing full symmetrical input ci rcuits with external coils. the following figures illustrate the new functionality. if one compares the relation z1 / z2, which is a measure for symmetry of the as-i module input towards machine ground, it becomes obvious that the new circuit is more symmetrical since z1 and z2 are more equal than in the conventional solution. please note, that this is not a complete application circuit. 2.3.2. ird communication channel besides the as-i communication channel the asi4u can also operate on a second input channel, the so called ird input channel or addressing channel. in this mode the ird pin is input for an as-i signal in manchester-ii-coded format. the signal can either be an ac-current signal generated by a photo diode or a 5v-cmos signal. the ic automatically detects the type of the signal and switches the input path accordingly. output pin in ird communication mode is led1. it transmits the slave response as inverted manchester-ii- coded as-i signal. the red led, which is normally conn ected to led1, can form the response transmitter in an optical communication system or led1 can be directly connected to some external circuitry. activation of the ird communication channel is achieved by a so called magic sequence that is sent in advance of the desired communication. the construction of a magic sequence is described in detail in chapter 3.3 addressing channel input ird on page 6. the ird communication mode is basically left by ic reset, except in one special case that is also described in that chapter . 2.3.3. parameter port pins the asi4u features a 4-bit wide parameter port and a related parameter strobe signal pin pst. there is a defined phase relation between a parameter output event, the parameter input sampling and the activation of the pst signal. thus it can be used to trigger external logic or a micro controller to process the received parameter data or to provide new input data for the as-i slave response. as-i complete specification v3.0 newly defines a bidirectional mode for parameter data. the asi4u supports this feature that can be activated by special e2prom setting. see chapter 3.6 parameter port and pst on page 6 for further details. asi+ asi- z2 z1 load as-i slave ic gnd figure 4: conventional application of as-i ic with one external coil figure 5: newly supported application of as-i ic with two external coils asi+ asi- z2 z1 load as-i slave ic gnd
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 18 of 63 2.3.4. data port pins an important feature of the asi4u is the 8-bit wide data port that consists of a 4-bit wide input section and a 4- bit wide output section. the input and output sections work independently from each other allowing a maximum of 8 devices (4 input and 4 output devices) to be connected to the asi4u. for special applications (compatibility), the so called multiplex mode can be activa ted that limits the output activation to a certain time frame. thus, a 4-bit wide bi-directional data i/o port can be realized by external connection of the corresponding data input and output pins. the data port is accompanied by the data strobe signal dsr. there is a defined phase relation between a data output event, the input data sampling and the activation of the dsr signal. thus, it can be used to trigger external logic or a micro controller to process the re ceived data or to provide new input data for the as-i slave response. see chapter 3.7 data port and dsr on page 6 for further details. 2.3.5. data input inversion by default the logic signal (high / low) that is presen t at the data input pins during the input sampling phase is transferred without modification to the send register, which is interfaced by the uart. by that, the signal becomes directly part of the slave response. some applications work with inverted logic levels. to avoid additional external inverters, the input signal can be inverted by the asi4u before transferring it to the send register. the inversion of the input signals can either be done bit selective or jointly for all data input pins. see chapter 3.7.2 input data pre-processing on page 6. 2.3.6. data input filtering to prevent input signal bouncing from being transferred to the as-i master, the data input signals can be digitally filtered. filter times can be configured in 7 step s from 128s up to 8.192ms. additionally there is a so called as-i cycle mode available. if activated, the filter time is determined by the actual as-i cycle time. for more detailed information refer to chapter 3.7.2 input data pre-processing on page 6. the filter function can be enabled bit selective. activa tion of the filters is done jointly either by e2prom configuration or by the logic state of parameter port pin p2. see chapter 3.7.2 input data pre-processing on page 6. 2.3.7. fixed data output driving the fixed data output driving feature is thought to ease board level design for similar products that do not require the full data output port width. the user can select one or more bits from the data output port to be driven by a distinct logic level instead by the data that was sent by the master. the distinct output data is stored in the e2prom and can be set during final module configuration. thus it is possible to signal the actual ic profile to some external circuitry and to allo w reuse of certain board designs for different product applications. see chapter 3.7.3 fixed output data driving on page 6 for further details. 2.3.8. synchronous data i/o mode as-i complete specification v3.0 newly defines a synchronous data i/o feature that allows a number of slaves in the network to switch their outputs at the same time and to have their inputs sampled jointly. this feature is especially useful if more than 4-bit wide da ta is to be provided synchronously to an application. the synchronization point was defined to the data exchange event of the slave with the lowest address in the network. this definition relies on the cyclical slave polling with increasing slave addresses per cycle that is one of the basic communication principles of as-i. the ic always monitors the data communication and detects the change from a higher to a lower slave address. if such a change was recognized, the ic assumes that the slave with the lower address has the lowest address in the network. there are some special procedures that become active during the start of synchronous i/o mode operation and if more than three consecutive telegrams were sent to the same slave address. this is described in more detail in chapter 3.7.4 synchronous data i/o mode on page 6.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 19 of 63 2.3.9. 4 input / 4 output processing in extended address mode a new feature of as-i complete specification v3.0 is also support of 4-bit wide output data in extended address mode. in extended address mode it was, up to complete specification v2.11, only possible to send three data output bits from the master to the slave because telegram bit i3 is used to select between a- and b- slave type for extended slave addressing (up to 62 slaves per network). in normal address mode i3 carries output data for pin d3. the new definition introduces a multiplexed data transfer, so that all 4-bits of the data output port can be used again. a first as-i cycle transfers the data for a 2-bit output nibble only, while the second as-i cycle transfers the data for the contrary 2-bit nibble. nibble selection is done by the remaining third bit. to ensure continuous alternation of bit information i2 and thus continued data transfer to both nibbles, a special watchdog was implemented that observes the state of i2 bit. the watchdog can be activated or deactivated by e2rpom setting. it provides a watchdog filter time of about 327ms. the multiplexed transfer of course increases the refresh time per output by a factor of two, however, some applications can tolerate this increase for the benefit of less external circuitry and better slave address efficiency. the sampling cycle of the data inputs remains unchanged since the meaning of i3 bit was not changed in the slave response with the definition of the extended address mode. more detailed information is described in chapter 3.7.5 support of 4i/4o processing in extended address mode, profile 7.a.x.e on page 6. 2.3.10. as-i safety mode the enhanced data input features described above require additional registers in the data input path that store the input values for a certain time before they hand them over to the as-i transmitter. this causes a time delay in the input path that could lead to a delayed ?turn off? ev ent, if the registers were activated by intention or by accident in as-i safety applications. to safely exclude an activation of the enhanced data i/o features in safety applications, the ic provides a special safety mode that is strongly recommended to be used for as-i safety communication purposes. see chapter 3.7.6 safety mode operation on page 6 for further details. 2.3.11. enhanced led status indication asi4u newly supports enhanced status indication by two le d outputs. a special mode for direct application of dual-leds and the respective different signaling modes is also implemented. compared to the a2si, the former u5rd pin was reassigned as led2 pin. thus, compatibility to existing a2si board layouts is still guaranteed. however, it will require to keep led2 pin disabled (default state at delivery) in order to avoid short-circuiting of u5r to ground. more detailed info rmation on the different signaling schemes and their activation can be found in chapter 3.9 led outputs on page 6. 2.3.12. communication monitor/watchdog data and parameter communication are continuously observed by a communication monitor. if neither data_exchange nor write_parameter calls were addressed to and received by the ic within a time frame of about 41ms, a so called no data/parameter exchange status is detected and signaled at led1. if the respective flags are set in the e2prom the communication monitor can also act as communication watchdog that initiates a complete ic reset after expiring of the watchdog timer. the watchdog mode can also be activated and deactivated by a signal at parameter port pin p0. for more detailed information see chapter 3.14 communication monitor/watchdog on page 6. 2.3.13. write protection of id_code_extension_1 as defined in as-i complete specification v3.0 the asi4u also supports write protection for id_code_exten- sion_1. the feature allows the activation of new manufacturer protected slave profiles and is enabled by e2prom setting. it is describ ed in more detail in chapter 3.16 write protection of id_code_extension_1 on page 6
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 20 of 63 2.3.14. summary of master calls table 6 on page 6 and the diagram at the following page show the complete set of master calls that are decoded by the asi4u in slave mode. the "enter program mode" call is intended for programming of the ic by the slave manufacturer only. it becomes deactivated as soon as the program_mode_disable flag is set in the firmware area of the e2prom. as-i complete specification compliance note: in order to achieve full compliance to the as-i complete specification, the program_mode_disable flag must be set by the manufacturer of as-i slave modules during the final manufacturing and configuration process and before an as-i slave device is delivered to field application users.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 21 of 63 table 6: asi4u master calls and related slave responses master request slave response instruction mne st cb a4 a3 a2 a1 a0 i4 i3 i2 i1 i0 pb eb sb i3 i2 i1 i0 pb eb data exchange dexg 0 0 a4 a3 a2 a1 a0 0 d3 ~sel d2 d1 d0 pb 1 0 d3 e3 d2 e2 d1 e1 d0 e0 pb 1 write parameter wpar 0 0 a4 a3 a2 a1 a0 1 p3 ~sel p2 p1 p0 pb 1 0 p3 i3 p2 i2 p1 i1 p0 i0 pb 1 address assignment adra 0000000a4a3a2a1a0pb1 0011001 write extented id code_1 wid1 01000000id3id2id1id0pb1 0000001 delete address dela 0 1 a4 a3 a2 a1 a0 0 0 sel 0 0 0 pb 1 0 0 0 0 0 0 1 reset slave res 0 1 a4a3a2a1a0 1 1 ~sel 100pb1 0011001 read io configuration rdio 0 1 a4 a3 a2 a1 a0 1 0 sel 0 0 0 pb 1 0 io3 io2 io1 io0 pb 1 read id code rdid 0 1 a4 a3 a2 a1 a0 1 0 sel 0 0 1 pb 1 0 id3 id2 id1 id0 pb 1 read id code_1 rid1 0 1 a4 a3 a2 a1 a0 1 0 sel 0 1 0 pb 1 0 id3 id2 id1 id0 pb 1 read id code_2 rid2 0 1 a4 a3 a2 a1 a0 1 0 sel 0 1 1 pb 1 0 id3 id2 id1 id0 pb 1 read status rdst 0 1 a4 a3 a2 a1 a0 1 1 ~sel 1 1 0 pb 1 0 s3s2s1s0pb 1 broadcast (reset) br01 0 1 1 1 1 1 1 1 0 1 0 1 1 1 --- no slave response --- enter program mode prgm 0 1 0 0 0 0 0 1 1 1 0 1 1 1 --- no slave response --- note: in extended address mode the "select bit" defines whether the a-slave or b-slave is being addressed. depending on the ty pe of master call bit i3 carries the select bit information (sel = a- slave) or the inverted select bit information (~sel = b-slave).
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 22 of 63 b-slave with profile 0.a (green shaded) asi master request (black/green) asi slave response (blue) no slave response (blue shaded) adr != 0 i2 i1 i0 000 001 010 011 100 101 110 111 cb i4 i3 i3=sel (slave address != 0) and (progam mode not activated) 000 sel=0 data_exchange /sel d2 d1 d0 001 sel=1 data_exchange d3 d2 d1 d0 d3 d2 d1 d0 010 sel=0 write_parameter /sel p2 p1 p0 011 sel=1 write_parameter p3 p2 p1 p0 p3 p2 p1 p0 100 sel=0 delete_addr x0 101 sel=1 delete_addr x0 110 sel=0 rd_io_cfg read_id read_id_1 read_id_2 reset_slave 0x6 broadcast rd_status 111 sel=1 rd_io_cfg read_id read_id_1 read_id_2 reset_slave 0x6 rd_status adr == 0 i2 i1 i0 000 001 010 011 100 101 110 111 cb i4 i3 (slave address == 0) and (progam mode not activated) 000 001 address_assignment a4 a3 a2 a1 a0 010 0x6 011 100 write_var_ext_code1 id3 id2 id1 id0 101 0x0 110 rd_io_cfg read_id read_id_1 read_id_2 broadcast 111 reset_slave 0x6 enterpmode rd_status i2 i1 i0 000 001 010 011 100 101 110 111 cb i4 i3 progam mode activated 000 001 data_exchange - - - - i3 i2 i1 i0 (eeprom read access) 010 011 write_parameter i3 i2 i1 i0 i3 i2 i1 i0 (eeprom write access) 100 write_var_id_code id3 id2 id1 id0 101 0x0 110 rd_io_cfg read_id read_id_1 read_id_2 reset_slave 0x6 broadcast rd_status reserved 111 rd_io_cfg read_id read_id_1 read_id_2 reset_slave 0x6 enterpmode rd_status reserved
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 23 of 63 2.4. master mode master mode and the related repeater- and monitor-modes differ completely in their functional properties from the slave mode. while the ic can autonomously perform different tasks in slave mode, it will only act as physical layer transceiver in master-, repeater- and monitor-mode. the basic property of these modes is a modulation / demodulation of as-i signals to manchester-ii-code and vice versa. the following figure shows the different data path configurations. master mode slave mode, asi-channel slave mode, ird addressing channel master-mode, repeater-mode and monitor-mode differ from each other in the kind of signals that are available at the data i/o and parameter port pins of the ic. following signal assignments are provided: pin master mode repeater mode monitor mode p0 receive clock hi-z receive clock p1 power fail hi-z power fail p2 receive strobe ? slave telegram hi-z receive strobe ? slave telegram p3 hi-z hi-z receive strobe ? master telegram di0 di1 inverting of ird input signal. if both inputs are on different level, the ird input signal is inverted before further processing, otherwise it is directly forwarded to the uart. di2 di3 inverting of led output signal. if both inputs are on different level, the led output signal is in- verted after processing, otherwise it is directly forwarded to the led1 output. do0 hi-z hi-z pulse code error do1 hi-z hi-z no information error do2 hi-z hi-z parity bit error do3 hi-z hi-z manchester-ii-code error at ird input more detailed signal descriptions can be found in chapters 3.6 parameter port and pst , 3.7 data port and dsr as well as 3.12 uart . asi- receiver asi- transmitter ird cmos input led output uart asi+ asi- ird (tx) led1 (rx) figure 6: data path in master-, repeater- and monitor-mode
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 24 of 63 2.5. e2prom the asi4u provides an on-chip e2prom with typical write times of 12.5 ms and read times of 110ns. for security reasons the memory area is structured in two independent data blocks and a single bit security flag. the data blocks are named user area and firmware area. the firmware area contains all manufacturing related configuration data (i.e. selection of operational modes, id codes, ?). it can be protected against undesired data modification by setting the program_mode_disable flag to ?1?. the user area contains only such data that is relevant fo r changes at the final application (i.e. field installation of slave module). the environment, where modifications of the user data may become necessary, can sometimes be rough and unpredictable. in order to ensure a write access cannot result in an undetected corruption of e2prom data, additional security is provided when programming the user area. any write access to the user area (by calls address_assignment or write_id_code1 ) is accompanied by two write steps to the security flag, one before and one after the actual modification of user data. the following procedure is executed when writing to the user area of the e2prom: 1. the security flag is programmed to ?1?. 2. the content of the security flag is read back, verifying it was programmed to ?1?. 3. the user data is modified. 4. a read back of the written data is performed. 5. if the read back has proven successful programming of the user data, the security flag is programmed back to ?0?. 6. the content of the security flag is read back, verifying it was programmed to ?0?. in addition to a read out of the data areas, the security flag of the e2prom is also read and evaluated during ic initialization. in case the value of the security flag equals ?1? (i.e. due to an undesired interruption of a user area write access), the entire user area data is treated as corrupted and the slave address is set to 0x0 in the corresponding volatile shadow registers during initialization. thus the programming of the user area data can be repeated. table 7: e2prom content asi4u internal e2prom address [hex] bit position eeprom cell content eeprom register content 0 0 ? 3 a0 ? a3 slave address low nibble 1 0 a4 slave address high nibble 2 0 ? 2 id1_bit0 ? id1_bit2 id_code_extension_1 2 3 id1_bit3 id_code_extension_1 , a/b slave selection in extended address mode 3 ? 7 not implemented 8 0 ? 3 id_bit0 ? id_bit3 id_code 9 0 ? 3 id2_bit0 ? id2_bit3 id_code_extension_2 a 0 ? 3 io_bit0 ? io_bit3 io_code 0 multiplex_data multiplexed bi-directional data port mode 1 multiplex_paramter multiplexed bi-directional parameter port mode 2 p0_watchdog_activation watchdog can be activated/deactivated by the logic value at parameter pin p0. watchdog_active must not be set. b 3 watchdog_active communication watchdog is continuously activated.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 25 of 63 asi4u internal e2prom address [hex] bit position eeprom cell content eeprom register content 0 master_mode if set, firmware area cannot be accessed. 1 program_mode_disable if set, firmware area is protected against overriding. 2 repeater_mode if set, firmware area cannot be accessed. c 3 invert_data_in all data port inputs are inverted. d 0 ? 3 di_invert_configuration enables separate input data inverting for selected di pins. invert_data_in must not be set. e 0 ? 3 di_filter_configuration enables unitary anti-bouncing filters for selected di pins 0 ? 2 di_filter_time_constant defines a time constant for the input filter. for coding rules see chapter 3.7.2. f 3 p1_filter_activation if flag is set, the logic value at the parameter pin p1 determines whether the filter function is active or inactive (see chapter 3.6.2.) if flag is not set, di_filter_configuration activates the filter function. 10 0 ? 3 data_out_configuration defines whether the corresponding data port output pin is driven by the data output register (sensitive to the data_exchange command) or the data_out_value register (e2prom configured). 11 0 ? 3 data_out_value stores static data port output value if selected by data_out_configuration 0 enhanced_status_indication if set, enhanced status indication mode according to as-i complete specification is activated. activates led2 output! for compatibility to a2si board layouts this flag must not be set (=?0?). 1 dual_led_mode if set, led1 and led2 output signals are controlled to comply with dual led indication schemes of as-i. generated signals depend also on value of enhanced_sta-tus_indication flag. direct connection of a dual led is supported. activates led2 output ! for compatibility to a2si board layouts this flag must not be set (= ?0?). 2 fid_invert the fid input value is inverted before further processing 12 3 safety_mode if set, the asi4u safety mode is enabled and a special data input routing is activated.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 26 of 63 asi4u internal e2prom address [hex] bit position eeprom cell content eeprom register content 0 synchronous_data_io enables synchronized data i/o mode 1 p2_sync_data_io_activation if flag is set, the logic value at the parameter pin p2 determines whether the synchonous data io mode is active or inactive. if flag is not set, the synchonous data io mode is always active if it was enabled by the synchronous_data_io flag. 2 ext_addr_4i/4o_mode enables 4 input / 4 output support in extended address mode 13 3 id_code1_protect if flag is set, id_code_extension_1 is write protected for user access. in extended address mode, only bits 2?0 are blocked. bit 3 is used for a/b slave selection and must remain user accessible. 14 0 ? 3 id1_bit0 ? id1_bit3 protected_id_code_extension_1 if id_code1_protect flag is set, an read_id_code_1 request will be answered with the data stored in this register. 15 0 ? 3 16 0 ? 3 17 0 ? 3 trim area, accessible by zmdi only user area firmware area
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 27 of 63 3 detailed functional description 3.1. as-i receiver the receiver detects (telegram) signals at the as-i line, converts them to digital pulses and forwards them to the uart for further processing. the receiver is internally connected between the asip and asin pins. it supports floating (ground free) input signals within the voltage limits of asip and asin given in table 2 at page 6. functional, the receiver removes the dc value of the inpu t signal, band-pass filters the ac signal and extracts the digital output signals from the sin 2 -shaped input pulses by a set of comparators. the amplitude of the first pulse determines the threshold level for all following pulses. this amplitude is digitally filtered to guarantee stable conditions and to suppress burst spikes. this approach combines a fast adaptation to changing signal amplitudes with a high detection safety. the comparators are reset after every detection of a telegram pause at the as-i line. when the receiver is turned on, the transmitter is turned off to reduce the power consumption. table 8: receiver parameters symbol parameter min max unit note v sig ac signal peak-peak amplitude (between asip and asin) 3 8 v pp v lsigon receiver comparator threshold level (refer to figure 7) 45 55 % related to 1st pulse amplitude 3.2. as-i transmitter the transmitter draws a modulated current between asip and asin to generate the communication signals. the shape of the current corresponds to the integral of a sin 2 -function. the transmitter comprises a current dac and a high current driver. the driver requires a small bias current to flow. the bias current is ramped up slowly a certain time before the transmission starts so that any false voltage pulses on the as-i line are avoided. to support high symmetry extended power applications as shown in figure 21 at page 6, the transmitter is designed to allow input voltages different from ic ground at the asin pin. the limits given in table 2 at page 6 apply. when the transmitter is turned on, the receiver is turned off to reduce the power consumption. table 9: transmitter current amplitude first negative pulse of the as-i telegram v lsigon v lsigon = (0.45 ... 0.55) * v sig / 2 the ic determines the amplitude of the first negative pulse of the as-i telegram. this amplitude is asserted to be v sig / 2. dc level v sig / 2 fi g ure 7: receiver com p arator threshold set - u p in p rinci p l e symbol parameter min max unit note i sig modulated transmitter peak current swing (between asip and asin) 55 68 ma p
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 28 of 63 3.3. addressing channel input ird 3.3.1. general slave mode functionality to ease the configuration process for slave modules at the field application, a secondary command input channel, the so-called addressing channel, ird, is provided. once the channel is activated for communication, the ird pin is receiving manchester-ii-coded (as-i) master telegrams, while the led1 pin is returning slave response telegrams in manchester-ii format. applying a so-called magic sequence at the ird input activates the addressing channel. it doesn?t matter whether the ic is communicating at the as-i input channel or staying in idle mode. as long as the initialization process is finished and the ic is operating in slave mode, a correctly received magic sequence will reset the data and parameter outputs, generate appropriate data strobe and parameter strobe signals, reset the data_exchange_disable flag and turn the addressing channel active. the magic sequence requires the reception of four consecutive correct as-i telegrams in manchester-ii- format within a timeframe of 8.192 ms (-6.25%). th e telegrams will neither be answered nor otherwise internally processed. they are only checked for correct syntax (number of bits, correct start bit, end bit and parity) and timing (compliance to standard as-i telegram timing). to avoid a wrong activation of the addressing channel by undesired cross coupling of signals from the as-i line to the ird input, two additional security features are implemented. 1. the asi4u resets the magic sequence telegram counter if more than 5 but less than 14 telegram bits were correctly received. pulse signals that lead to detection of a communication error before the 6 th telegram bit shall not reset the magic sequence counter in order to avoid a blocking of the ird activation due to signal bouncing effects. 2. the asi4u resets the magic sequence telegram counter if a telegram that was received at the ird input correlates to the as-i line input signal in terms of telegram reception time and content. note: the uart processes both input channels (as-i line + ird addressing channel) in parallel and generates receive_strobe signals after every correctly received master telegram. a telegram correlation between both channels is found, if receive_strobe signals from both input channels arrive at a time frame of less or equal than 3s and the telegram contents are equal too. the addressing channel generally becomes deactivated by ic reset. if the ic is locked to the addressing channel and ac current input mode (see descriptions further below) is active, there are four special ic functions that were implemented to support existing handheld programming devices (from the company pepperl+fuchs): 1. the ic does not leave the addressing channel mode after the reception of a reset_slave or broadcast_reset call if the data_exchange_disable flag is cleared (?0?). this is always the case if the asi4u had performed data-/parameter communication in advance of the reset. thus the handheld had been operated in data- or parameter mode. 2. the ic does not leave the addressing channel during an ic reset that was caused by an expired communication watchdog. see chapter 3.14 for detailed descriptions of the communication monitor and communication watchdog . 3. software controlled ic resets (resets through reset_slave or broadcast_reset calls) are performed slightly different than in normal slave ic operation. the ic still resets the data and parameter outputs immediately after reception of the calls and data- and parameter-strobe signals are generated. however, the ic initialization procedure is postponed for 2.048ms (-6.25%), keeping the ic blocked to any further telegram inputs at the addressing channel or the as-i line input. this is to avoid an immediate reactivation of the addressing channel after ic initialization since the handheld programming device always sends five subsequent broadcast_reset . the asi4u would otherwise process the first reset call from the handheld correctly but take the four remaining calls for a new magic sequence.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 29 of 63 4. the uart is constantly set to synchronous receive mode. this is because the signal sequence that is generated by the handheld programming device exhibits an additional signal transition in a time frame of 3 bit times after the end of the transmitted master call. 3.3.2. ac current input mode the ird input allows direct connection of a photo-diode (referencing to 0v) and senses the generated photo current. a valid input signal has to have certain current amplitude (range) and must not exceed a certain offset current value (table 10 and figure 8). in contrast to a2si versions, the ird input of the asi4u covers the entire input current range by a single amplifying stage with continues (logarithmical) gain adaptation. thus, the cyclical gain switching is avoided and the ic can react more safely and without delay on different input signal amplitudes. table 10: ird ac current input parameters symbol parameter min max unit note i irdo input current offset 10 a i irda input current amplitude 25 100 a min i irda max i irda max i irdo time ird input current figure 8: addressing channel input (ird), photo-current waveforms following photo-diode is suggested for optimal performance: ? temic temd5000 3.3.3. cmos input mode in addition to the ac current input mode, the ird input can also operate in cmos input mode. mode switching is only possible as long as the ic has not locked to the addressing channel by reception of a magic sequence already. on principle, that input mode that lead to th e activation of the addressing channel will remain locked until the addressing channel is deactivated (by ic reset). the cmos mode is entered if the ird input voltage is above 2.5v (logic high) for more than 7.680 ms (- 6.66%). it is left, if the ird input voltage is below 1.0v (logic low) for more than 7.680 ms (-6.66%). the initial input mode after ic initialization is determined at the end of the initialization phase and depends on the value of the ird input signal at that time.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 30 of 63 table 11: ird current/voltage mode switching symbol parameter min max unit note v ird_vm minimum ird input voltage to activate cmos mode of ird 2.5 v v ird_cm maximum ird input voltage to activate ac current mode of ird 1.0 v t ird_mode_filter filter time constant for ird input mode switching 7.68 8.192 ms the following input levels apply in cmos mode: table 12: ird cmos input levels symbol parameter min max unit note v ird_in input voltage range -0.3 v uout v v ird_il voltage range for input ?low? level 0 1.0 v v ird_ih voltage range for input ?high? level 2.5 v uout v t r /t f rise/fall time 100 ns 1 1 in master mode the rise/fall time of the ird input signal should be as low as possible in order to avoid jitter on the as-i line 3.3.4. master-, repeater- and monitor-mode in master-, repeater-, and monitor-mode the ird input is always configured in cmos mode. the input levels specified in table 12 apply. the expected polarity of the manchester-ii-coded bit stream at the ird pin depends on the values of the pins di0 and di1. table 13: polarity of manchester-ii-signal at ird in master mode input values at di0 and di1 are: description equal (?11?, ?00?) manchester-ii-signal is low active (default logic output value at no communication is ?1?). this mode is compatible to the a2si ird input unequal (?01?, ?10?) manchester-ii-signal is high active (default logic output value at no communication is ?0?). note: the complemented definition was chosen to retain backward compatibility to a2si based as-i master designs.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 31 of 63 3.4. digital inputs - dc characteristics the following pins contain digital high voltage input stages: - input-only pins: di0 ? di3, fid - i/o pins: p0 ? p3, dsr, pst 1 , led2 1 table 14: dc characteristics of digital high voltage input pins symbol parameter min max unit note v il voltage range for input ?low? level 0 2.5 v v ih voltage range for input ?high? level 3.5 v uout v v hyst hysteresis for switching level 0.25 v i il current range for input ?low? level -10 -3 a 2 i ih current range for input ?high? level -10 10 a v 0 ? v u5r c dl capacitance at pin dsr 10 pf 3 1 pst and led2 are inputs for test purposes only. 2 the pull-up current is driven by a current source connected to u5r. it stays almost constant for input voltages ranging from 0 to 3.8v. the current source is disabled at the fid pin in master- repeater- and monitor-mode to provide a straight analog signal input for the power fail comparator. 3 the internal pull-up current is sufficient to avoid accidental triggering of an ic reset if the dsr pin remains unconnected. for external loads at dsr a certain pull up resistor is required to ensure v ih ? 3.5v in less than 35s after the beginning of a dsr = low pulse. 3.5. digital outputs - dc characteristics the following pins contain digital high voltage open drain output stages: - output-only pins: do0 ? do3, led1 - i/o pins: p0 ? p3, dsr, pst 1 , led2 1 table 15: dc characteristics of digital high voltage output pins symbol parameter min max. unit note v ol1 voltage range for output ?low? level 0 1 v i ol1 = 10ma v ol2 voltage range for output ?low? level 0 0.4 v i ol2 = 2ma i oh output leakage current -10 10 a v 0h ? v u5r v oh voltage range for output ?high? level (external applied voltage) v uout v 1 pst and led2 are inputs for test purposes only.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 32 of 63 3.6. parameter port and pst pin 3.6.1. slave mode the parameter port is configured for continuous bi-dir ectional operation. every pin contains an nmos open drain output driver plus a high voltage high impedance digital input stage. received parameter output data is stored at the parameter output register and subsequently forwarded to the open drain output drivers. a certain time (t pi-latch ) after new output data has arrived at the port, the corresponding inputs are sampled. the input value either results from a wired and combination of the parameter output value and the signals driven to the port by external sources ( multiplex_parameter =?0?) or simply represents the externally driven input signals ( multiplex_parameter =?1?). for further explanation see also figure 9 and chapter 3.6.2. the availability of new parameter output data is signaled by the parameter strobe (pst) signal . besides the basic i/o function, the first parameter output event after an ic reset has an additional meaning. it enables the data output at the data port (see chapters 3.7 and 3.11). any ic reset or the reception of a delete_address call turns the parameter output register to 0xf and forces the parameter output drivers to high impedance state. simultaneously a parameter strobe is generated, having the same t setup timing and t pst pulse width, as new output data would be driven. table 16: timing parameter port symbol parameter min max unit note t setupl output data is valid low before pst-h/l 0.1 0.6 s 1 t setuph output driver is at high impedance state before pst-h/l 0.1 0.6 s 1 t hold output driver is at high impedance state after pst-h/l 0.1 0.6 s 1, 2 t pst pulse width of parameter strobe (pst) 5 6 s 3 t pi-latch acceptance of input data 11 13.5 s 4 1 the designed value is 0.5s. 2 t hold is only valid, if the multiplex_parameter flag is set in the firmware area of the e2prom. 3 the timing of the resulting voltage signal also depends on the external pull up resistor. 4 the parameter input data must be stable within the period defined by min. and max. values of t pi-latch . pst t setup t pst t pi-latch parameter port output data keep stable min max p0..p3 pi0..pi3 parameter port input data t hold data remains constant, if multiplex_parameter flag is not set hi-z, if multiplex_parameter flag is set figure 9: timing diagram parameter port p0 ... p3, pst
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 33 of 63 3.6.2. parameter multiplex mode as-i complete specification v3.0 defines a so called parameter multiplex mode. this new feature allows bi- directional data transfer through the parameter port. the bi-directionality is achieved by turning the parameter output drivers off after the parameter strobe period and before the input sampling event. by turning off its output drivers during the parameter strobe pulse, an ex ternal microcontroller can read the data from the parameter port of the asi4u, prepare new return data an d place it to the port right after the parameter strobe signal. the parameter multiplex mode becomes activated by setting the corresponding multiplex_parameter flag (=?1?) in the e2prom. to keep full compatibility to a2si based applications this flag should be kept zero (=?0?). the a2si did not allow real bi-directional parameter data transfer since it was no t able to turn the output drivers off. the return value to a write_parameter call was always a wired and combination of the output signal of the ic and the signal driven to the port by the external logic. 3.6.3. special function of p0, p1 and p2 in case the watchdog_active flag is not set (=?0?) but the p0_watchdog_activation flag is set (= ?1?, firmware area of the e2prom) the value of the parameter port signal p0 determines whether the communication watchdog is enabled or disabled. in compliance to slave profile 7d-5 the behavior is defined as follows: input value at p0 state of communication watchdog low level (=?0?) disabled high level (=?1?) enabled if the p1_filter_activation flag is set in the e2prom, the activation of the data input filters depends on the value of the parameter port signal p1. following coding applies: input value at p1 data input filter function low level (=?0?) activated high level (=?1?) deactivated for further details refer to chapter 3.7 data port and dsr ? input data pre-processing. if the synchronous_data_i/o_mode flag is set in the e2prom, the value of the parameter port p2 activates or deactivates the synchronous data i/o mode of the asi4u. following coding applies: input value at p2 synchronous data i/o mode low level (=?0?) activated high level (=?1?) deactivated for further details refer to chapter 3.7 data port and dsr ? synchronous data i/o mode. the processed values of p0, p1 and p2 result from a wired-and combination between the corresponding output value and the input value driven by an external signal source.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 34 of 63 3.6.4. master-, repeater-, monitor mode in master-, repeater- and monitor mode the parameter port is differently configured than in slave mode. the pins serve as output channels for additional support signals or become set to high impedance state. there is no input function associated with the parameter port pins. following support signals are provided at the parameter port in master-, repeater- and monitor-mode. table 17: parameter port output signals in master-, repeater-, monitor-mode pin master mode repeater mode monitor mode p0 receive clock hi-z receive clock p1 power fail hi-z power fail p2 receive strobe ? slave telegram hi-z receive strobe ? slave telegram p3 hi-z hi-z receive strobe ? master telegram receive clock is provided to simplify external processing of manchester-ii-coded output data at led1 pin. the availability of a new as-i telegram bit at led1 is signaled by a rising edge of receive clock so that the received data can simply be clocked into a shift register. the output signal is active high. power fail signals a breakdown of the as-i supply voltage. the output signal is active high. further information regarding the power fail function refer to chapter 3.8 fault indication input pin fid. receive strobe ? slave telegram is generated after every correctly received as-i slave telegram. the output signal is active high. receive strobe ? master telegram is generated after every correctly received as-i master telegram. the output signal is active high. the generated pulse width is 1.0s for both receive strobe signals at the output drivers (hi-z time). the resulting signal pulse width depends on the external pull-up resistor and the load circuit.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 35 of 63 3.7. data port and dsr pin 3.7.1. slave mode the data port is divided in 4 output and 4 input pins. this makes it possible to control a maximum of 8 binary devices (4 input + 4 output devices) by a single as-i slave ic. compatibility to multiplexed bi-directional operation, as it is defined in certai n io configurations for as-i slaves, can be achieved by external connection of corresponding di and do pins and setting multiplex_data flag =?1? in the firmware area of the e2prom. every output pin (do0?do3) contains an nmos open drain output driver; every input pin (di0?di3) contains a high voltage high impedance input stage. received output data is stored at the data output register and subsequently forwarded to the do-pins. a certain time (t di-latch ) after new output data was written to the port, the di-pins are sampled. the availability of new output data is signaled by the data strobe (dsr) signal as shown in figure 10. the dsr pin has an additional reset input func tion, that is described further in chapter 3.11 ic reset. table 18: timing data port outputs symbol parameter min max unit note t setupl output data is valid low before dsr-h/l 0.1 0.6 s 1 t setuph output driver is at high impedance state before dsr-h/l 0.1 0.6 s 2 t hold output driver is at high impedance state after dsr-h/l 0.1 0.6 s 1, 2 t dsr pulse width of data strobe (dsr) 5 6 s 3 t di-latch acceptance of input data 11 13.5 s 4 1 the designed value is 0.5s. 2 parameter is only valid if multiplex_data flag is set in the firmware area of the e2prom. 3 the timing of the resulting voltage signal also depends on the external pull up resistor. 4 the input data must be stable within the pe riod defined by min. and max. values of t di-latch . dsr t setup t dsr t di-latch data port output data keep stable min max do0..do3 di0..di3 data port input data t hold data remains constant, if multiplex_data flag is not set hi-z, if multiplex_data flag is set figure 10: timing diagram data port do0 ... do3, di0 ? di3, dsr
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 36 of 63 any ic reset or the reception of a delete_address call turns the data output register to 0xf and forces the data output drivers to high impedance state. simultaneously a data strobe is generated, having the same t setup timing and t dsr pulse width, as new output data would be driv en. all data port operations as well as the generation of a slave response to data_exchange (dexg) requests depend on the value of data_exchange_disable flag. it becomes set during ic reset or after a delete_address call prohibiting any data port activity after ic initialization or address assi gnment, as long as the external circuitry was not pre- conditioned by dedicated parameter output data. the data_exchange_disable flag is cleared while processing a write_parameter (wpar) request. consequently the as-i master has to send a wpar call in advance of the first data_exchange (dexg) request in order to enable data port operation at the slave. 3.7.2. input data pre-processing besides the standard input function the data port offers different data pre-processing features that can be activated by setting corresponding flags in the firmware area of the e2prom. the data path is structured as follows: joint input inverting the input values of all four data input channels are inverted when the invert_data_in flag is set. any configurations made in the di_invert_configuration register are ignored. the feature is kept for compatibility with a2si product versions. ? selective input inverting if the invert_data_in flag is not set, inverting of input data can be configured individually for every data port input channel by setting the corresponding flag in the di_invert_configuration register. hereby the index of the di channel corresponds to the bit position within the register. thus, the data at input channel di0 is inverted if bit 0 of the di_invert_configuration register is set and consequently input channel di3 is inverted if bit 3 is set. ? selective input filtering a digital anti-bouncing filter is provided at every data input channel to keep undesired signal bouncing at the di pins away from the as-i master. if activated, a signal transition at the particular di pin is passed to the data input register only if the new value has remained constant for a certain time. input signal filter output start filter timer reset filter timer filter timer active filter timer expired figure 12: principle of input filtering data i/o controller + data input register configurable input inverter configurable input filter as-i transmitter fi g ure 11: in p ut p ath at data port
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 37 of 63 the filter time can be adjusted jointly for all input channels in seven steps by programming the di_filter_time_constant register in the firmware area of the e2prom. the following coding table applies: table 19: data input filter time constants di_filter_time_constant, tolerance = - 6.25% 0 1 2 3 4 5 6 7 corresponding input filter time constant 128 s 256 s 512 s 1024 s 2048 s 4096 s 8192 s as-i cycle if as-i cycle mode is selected, a new input value is returned to the master if equal input data was sampled for two consecutive data_exchange cycles. as long as the condition is not true, previous valid data is returned. to suppress undesired input data validation in case of immediately repeated data_exchange calls (i. e. as-i masters immediately repeat one data_exchange requests if no valid slave response was received on the first request) input data sampling is blocked for 256s (-6.25%) after every sampling event in as-i cycle mode. the di_filter_configuration register provides channel selective enabling of input filters; just as the di_invert_configuration register allows individual inverting of the four data port input channels. again, the index of the di channel corresponds to the bit position within the register. thus, data at input channel di0 is filtered if bit 0 of the di_filter_configuration register is set and consequently input channel di3 is filtered if bit 3 is set. in general the data input filters become active, as the corresponding bit in the di_filter_configuration register is set. ? they are initialized with ?0? and the filter timer is reset after the initialization phase of the ic. (the first is because an as-i master interprets data inputs at ?0? to be inactive.) ? if the p1_filter_activation flag is set to ?1?, the filters will also start to run after the initialization phase, however the data to construct the slave response is either taken from the actual data input values or the filtered values, depending on the state of parameter port p1 table 20: input filter activation by parameter port pin p1 p1_filter_activation flag parameter p1 data input filter function 0 don?t care on, active filters depend on di_filter_configuration 1 1 off 1 0 on, active filters depend on di_filter_configuration input signal filter output sampling point figure 13: principle of as-i cycle input filt ering (exemplary for slave with address 1) < 256 s (-6.25%) > 256 s (-6.25%) dexchg addr 1 dexchg addr1 dexchg addr 1 slave slave slave this sampling event is blocked to avoid immediate input data validation.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 38 of 63 if the ic is operated in parameter multiplex mode (see descriptions in chapter 3.6.1 and 3.6.2 on page 6 et sqq. ) while the p1_filter_activation flag is set, the parameter multiplex mode remains disabled for parameter port pin p1. this is to avoid erroneous deactivation of the input filters if no external driver is connected. input data inverting and input data filtering are independe nt features that can be combined as required by the application. programming the following e2prom flags or registers activates them: table 21: e2prom configuration for different input modes input mode e2prom flag or register name standard input joint input inverting selective input inverting selective input filtering invert_data_in 0 1 0 di_invert_configuration 0x0 don?t care 0x1 ? 0xf input inverting is additionally possible di_filter_configuration 0x0 0x1 ? 0xf di_filter_time_constant don?t care input filtering is additionally possible 0x0 ? 0x7 3.7.3. fixed output data driving besides the standard output function the data output port provides an additional function to drive a fixed output value that is stored in the firmware area of the e2prom. this feature is basically meant to support signaling of different firmware area setups to outside slave module circuitry. it presumes the application does not require all four data output pins. the e2prom data_out_configuration register is used to determine whether the corresponding data port output signal is sensitive to data_exchange calls, or if the driven data output value is taken from the corresponding bit in the data_out_value register, also located in the firmware area of the e2prom. the index of the do signal corresponds to the bit position in the data_out_configuration and data_out_value registers. the fixed outpu t driving capability is ac tivated if the particular data_out_configuration bit is set to ?1?. the standard output mode is activated if data_out_configuration is programmed to 0x0, which is the default state of the register. 3.7.4. synchronous data i/o mode as defined in the as-i complete specification, a master successively polls the network rising the slave addresses from the lowest to the highest. hence, data input and output operations normally take place at different times in different slaves. to support applications that require simultaneous data i/o operations on a certain number of slaves in the network, a synchronous data i/o mode is provided. the feature is enabled if the synchronous_data_io flag is set in the firmware area of the e2prom (=?1?). activation of the feature additionally depends on the value of the p2_sync_data_io_activation flag. following coding applies: table 22: activation states of synchronous data io mode synchronous_data_io flag p2_sync_data_io_activation flag input value at p2 synchronous data i/o mode 0 don?t care don?t care deactivated 1 0 don?t care activated 1 1 low level (=?0?) activated 1 1 high level (=?1?) deactivated the parameter port signal p2 is sampled at the rising edge of the data strobe (l/h transition) signal to determine the data i/o behavior at the next data output event.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 39 of 63 if the ic is operated in parameter multiplex mode (see description in chapter 3.6.1 on page 6 ) while synchronous_data_io flag and p2_sync_data_io_activation flag are set, the parameter multiplex mode remains disabled for parameter port pin p2. this is to avoid erroneous deactivation of the synchronous data io mode in case no external driver is connected. once activated, input data sampling as well as output data driving events are moved to different times synchronized to the polling cycle of the as-i network. nevertheless, the communication principles between master and slave remain unchanged compared to regular operation. following rules apply: ? data i/o is triggered by the dexg call to slave with the lowest slave address in the network. based on the fact, that a master is calling slaves successively with rising slave addresses, the asi4u considers the trigger condition true, if the slave address of a received dexg call is less than the slave address of the previous (correctly received) dexg call. data i/o is only triggered, if the slave has (correctly) received data during the last cycle. if the slave did not receive data (i.e. due to a communication error) the data outputs are not changed and no data strobe is generated (arm+fire principle). the inputs however, are always sampled at the trigger event. ? if the slave with the lowest address in the network is operated in the synchronous data i/o mode , it postpones the output event for the received data for a full as-i cycle. this is to keep all output data of a particular cycle image together. note: to make this feature useful, the master shall generate a data output cycle image once before the start of every as-i cycle. the image is derived from the input data of the previous cycle(s) and other control events. if an as-i cycle has started, the image shall not change anymore. in case a- and b- slaves are installed in parallel at one address, the master shall address all a-slaves in one cycle and all b-slaves in the other cycle. the input data, sampled at the slave with the lowest slave address in the network, is sent back to the master without any delay. thus, the input data cycle image is fully captured at the end of an as-i cycle, just as in networks without any synchronous data i/o mode slaves. in other words, the input data sampling point has simply moved to the beginning of the as-i cycle for all synchronous data i/o mode slaves. ? the first dexg call that is received by a particular slave after the activation of the data port ( data_exchange_disable flag was cleared by a wpar call is processed like in regular operation. this is to capture decent input data for the first slave response and to activate the outputs as fast as possible. the data i/o operation is repeated together with the i/o cycle of the other synchronous data i/o mode slaves in the network at the common trigger event. by that, the particular slave has fully reached the synchronous data i/o mode. ? if the p2_sync_data_io_activation flag is set to ?1? at the slave with the lowest address in the network, one data output value is lost when the synchronous data i/o mode is turned off (l/h transition at p2), while the value that is received in the cycle when the ic detects a signal change at p2 (h/l transition) is repeated. this particul ar behavior is caused by the fact that in synchronous data i/o mode the data output at the slave with the lowest address is postponed for a full as-i cycle (see description above). ? to avoid a general suppression of data i/o in the special case that a slave in synchronous data i/o mode receives dexg calls only to its own address (i.e. employment of a handheld programming device), the synchronous data i/o mode is turned off, once the asi4u receives three consecutive dexg calls to its own slave address. the ic resumes to synchronous data i/o mode operation after it observed a dexg call to a different slave address than its own. the reactivation of the synchronous data i/o mode is handled likewise for the first d exg call after activation of the data port (see description above). the data strobe (dsr) signal is of course also generated in synchronous data i/o mode . the timings of input sampling and output buffering correspond to the regular operation (refer to figure 10 and table 18).
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 40 of 63 3.7.5. support of 4i/4o processing in extended address mode, profile 7.a.x.e in extended address mode the information bit i3 of the as-i master telegram is used to distinguish between a- and b-slaves that operate in parallel at the same as-i slave address. for more detailed information refer to as-i complete specification. besides the benefit of an increased address range, the cycle time per slave is increased in extended address mode from 5 ms to 10 ms and the useable output data is reduced from 4 to 3 bits. because of the later, extended address mode slaves can usually control a maximum of 3 data outputs only. the input data transmission is not effected since the slave response st ill carries 4 data information bits in extended address mode. applications that require 4 bit wide output data in extended address mode, but can tolerate further increased cycle times (i.e. push buttons and pilot lights), shall be di rectly supported by a new slave profile 7.a.x.e that is defined in the as-i complete specification v3.0. if the ic is operated in extended address mode and the ext_addr_4i/4o_mode flag is set (=?1?) in the e2prom, it treats information bit i2 as sele ctor for two 2-bit wide data output banks ( bank_1, bank_2 ). a master shall transmit data alternating to bank_1 and bank_2 , toggling the information bit i2 in the respective master calls. the asi4u triggers a data output event (modification of the data out put ports and generation of data strobe) only at a data_exchange call that contains i2=?0? and if the asi4u received a data_exchange call with i2=?1? in the previous cycle. thus, new output data is issued at the data port synchronously for both banks at a falling edge of i2. the i2 toggle detector starts on state i2=?0? after reset. input data is captured and returned to the master at every cycle, independent of the value of information bit i2. in consequence the cycle time is different for input data and output data: - data input values become refreshed in the master image in less than 10 ms - data output values become refreshed at the slave in less than 21 ms following coding applies: table 23: meaning of master call bits i0 ? i3 in ext_addr_4i/4o_mode bit in master call operation / meaning i0 i1 if i2 = ?1? then i0/i1 are directed to temporary data output registers do0_tmp/do1_tmp if i2 = ?0? then i0/i1 are directed to the data output registers do2/do3 and do0_tmp/do1_tmp are directed to the data output registers do0/do1 i2 i2: /sel-bit for transmission to bank_1 (do0/do1) / bank_2 (do2/do3) i3 i3: /sel-bit for a-slave/b-slave addressing 3.7.6. safety mode operation the enhanced data input features described above require additional registers in the data input path that store the input values for a certain time before they hand them over to the as-i transmitter. this causes a time delay in the input path and would lead to a delayed ?turn off? event in as-i safety applications, which in turn results in an increase in safety reaction time of the application. to safely exclude an activation of the enhanced data i/o features in safety applications, a special safety mode of the ic must always be selected once the asi4u is used for safe as-i communication purposes. the safety mode is activated by setting the safety_mode flag in the firmware area of the e2prom. the safety mode contains the following properties: ? additional multiplexer an additional 2:1-multiplexer is added in front of the send multiplexer that is controlled by the safety_mode flag. for deactivated safety mode, the regular data path is active. ? exchange of data inputs the internal data paths of d3 and d2 are exchanged in safety mode and have to be exchanged in the external code generator that controls the data inputs of the asi4u as well. in case the safety mode
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 41 of 63 became accidentally deactivated by a hardware fault, an exchange of the bits would be recognized after 4 cycles in a running application (see figure 14). ? inverter at the data inputs in safety mode it is still possible to use the data i nput invert functionality (either joint input inverting or bit selective input inverting) of the ic. this allows to transform the default signal level of the external application (either high or low) to the requir ed default input level for as-i safety. for safety considerations there is no difference whether the inverter is integrated in the asi4u ic or added externally. an error in the inverter or inverter activation will be recognized by a running application within the next cycle. the following feature descriptions relate to the logica l signals after the (optional) data input inverters. important note: as described above, the pin assignment of di2 and di3 is exchanged in safety mode. however, the configuration register for selective input inverting is directly associated with the physical ic ports and is not changed. thus, in safety mode bit3 of the di_invert_configuration register defines the inverting of the logical signal di2 and bit2 defines the inverting the signal di3. ? modification of code sequence the transmitted value for d0 is calculated according to the following equation: d0 = d0 xor (d1 and d2 and d3) thus, the asi4u will generate ?1110? from the in put value ?1111? and ?1111? from the input value ?1110?. to comply with the coding rules of the safe as-i communication, which prohibit ?1111? as a valid state in the data stream, the external code generator has to store ?1111? instead of ?1110?. in case the safety mode became accidentally deactivated by an hardware fault, the ic would not perform the d0 combination anymore. the safety monitor would notice this as an error by reception of ?1111?, see figure 15. ? deactivation of the standard data path theoretically, the safety mode could become deactivate d for a single bit only, if a (single) fault occurs at one of the multiplexers. this would lead to code sequences where three bits are routed in the safety path and the fourth bit is routed in the standard path. therefore, an additional or-gate is added in the standard path, that ties the standard path to constant ?1? once the safety mode is activated. a valid data transfer in standard mode or safety mode is only possible, if all four multiplexers are switched to the same direction. any other state will be recognized by the safety monitor. ? activation of data_exchange_disable the data_exchange_disable flag is set by the ic after reset and will be cleared after the first parameter call. as long as the flag is set, the ic does not respond to data_exchange calls. in case the safety mode is activated and the synchronous_data_io flag or any of the di_filter_configuration flags are set in the firmware area of the e2prom, the data_exchange_disable flag cannot be cleared. this prevents any data communication in that particular case. see figure 16. following flow charts are valid in safety mode of the asi4u: note: >=1 represents a logical or =1 represents a logical xor & represents a logical and
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 42 of 63 di[n] filter sync >=1 di[m] safety_mode sync_enable filter_enable 1 0 0 1 1 0 send mux command to uart /safety_mode invert_di[n] =1 invert_di[m] =1 n = 3,2,1 m = 2,3,1 figure 14: flowchart - input d3 (d2,d1) in safety mode the ic contains only one single inverter that generates the inverted safety mode signal for all necessary purposes.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 43 of 63 di0 filter sync >=1 safety_mode sync_enable filter_enable 1 0 0 1 1 0 send mux command to uart /safety_mode & =1 =1 =1 =1 =1 invert_di0 invert_di3 invert_di2 invert_di1 di3 di2 di1 figure 15: flowchart - input d0 in safety mode 0
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 44 of 63 safety_mode sync_enable filter_enable data_exchange_disable >=1 & figure 16: flowchart - data_exchange_disable 3.7.7. master-, repeater-, monitor mode in master-, repeater- and monitor mode the data input and data output ports are differently configured than in slave mode. following control signals are provided at the data input port in master-, repeater- and monitor mode: table 24: control signal inputs in master-, repeater- and monitor mode data input port signal name description di0 invert_ird_a di1 invert_ird_b if the signals invert_ird_a and invert_ird_b are unequal, the ird input signal is inverted before further processing. see table 13. di2 invert_led1_a di3 invert_led1_b if the signals invert_led1_a and invert_led1_b are unequal, the led1 output signal is inverted after processing. see table 28. note: the complemented definition was chosen to retain backward compatibility to a2si based as-i master designs. the data output port is exclusively used in monitor mode to provide additional uart error signals. the signals are defined active low and will be set immediately after a telegram error was detected. they become reset at the beginning of the next telegram. following signals are available: table 25: error signal outputs in monitor mode data port output uart error signal description do0 plscod_err pulse code error indicates faulty as-i pulses. this is a disjunction of alternation error, start bit error, end bit error do1 no_info_err no information error length error the output signal is a disjunction of no_information_error and length_error as defined in the complete spec 3.0. the monitor mode does not distinguish between synchronized and not synchronized uart mode. there is always only one bit time supervised after the end of a telegram. do2 parb_err parity bit error received parity bit does not match the check sum calculated by the uart do3 ird_man_err man-ii-code error at ird input signal at ird input violates man-ii-coding rules 3.7.8. special function of dsr besides of its standard output function the data strobe pin serves as external reset input for all operational modes of the ic. pulling the dsr pin low for more than a minimum reset time generates an unconditioned reset of the ic, which is immediately followed by a re-initialization of the ic (e2prom read out). further information on the ic reset behavior, especially in regard to the signal timing, can be found at chapter 3.11 ic reset .
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 45 of 63 3.8. fault indication input pin fid 3.8.1. slave mode the fault indication input fid is provided for sensing a periphery fault-messaging signal in slave mode. it contains a high voltage high impedance input stage that influences the status bit s1 of an as-i slave directly. dc properties of the pin are specified at table 14: dc characteristics of digital high voltage input pins . if the fid_invert flag (firmware area of the e2prom) is not set , a periphery fault is signaled by logic high at the fid input. in this case s1 and fid are logically equiv alent, which is the default state. in the opposite case, when fid_invert = ?1?, the fid input value is inverted before any further processing. the fid_invert feature was added to provide special support for certain fault conditions. signal transitions at the fid pin become visible in s1 with a slight delay, because a clock synchronizing circuit is in between. 3.8.2. master- and monitor mode in master- and monitor mode the fid input provides a voltage sense comparator for power fail detection. its threshold voltage is set to 2.00 v +/-3%. a power fail event is recognized and displayed at the parameter pin p1 if the input voltage falls below the reference voltage for more than 0.7...0.9 ms. no power fail signal is generated while the ic is performing its initialization procedure. table 26: power fail detection at fid (master mode and monitor mode) symbol parameter min max unit note v fid-pf fid reference voltage to detect power fail 1.94. 2.06 v 1 r in-fid input resistance of fid input 2 meg ohms t loff power supply break down time to generate a power fail signal 0.7 0.9 ms 1 for the measurement for the as-i-voltage an external voltage divider is necessary, see application notes.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 46 of 63 3.9. led outputs 3.9.1. slave mode the asi4u provides two led pins for enhanced status indication. led1 and led2 both contain nmos open drain output drivers. in addition, led2 contains a high voltage high impedance input stage for purposes of the ic production test. for compatibility to a2si board layouts, where pin number 23 (former u5rd) had to be connected to u5r, the led2 function is turned off by default , keeping led2 always at high impedance state. this is to protect led2 against shorting the 5v supply (u5r ) to ground. led2 will be activated if the enhanced_status_indication flag and/or the dual_led_mode flag are set in the e2prom. in order to comply with the signaling schemes defined in the as-i complete specification a red led shall be connected to led1 and a green led shall be connected to led2. direct operation of a dual led is also supported but requires the dual_led_mode flag to be set. this is because led1 and led2 need to be controlled differently for as-i compliant dual led signaling. following status indication is supported table 27: led status indication symptom standard status indication extended status indication note normal dual led normal dual led power off no power supply available normal operation data communication is established no data exchange the data_exchange_disable flag is still set, prohibiting data port communication. ic is waiting for a write_parameter request. the communication monitor has detected no data exchange status or the ic was reset by watchdog ic reset. no data exchange (address = 0) slave is waiting for address assignment. data port communication is not possible. periphery fault alternating alternating periphery fault signal generated at fid input. serious periphery fault with reset alternating data strobe driven low for more than 44s. the flashing frequency of any flashing status indication is around 2 hz . green red green green red green gree n red gree n gree n red gree n green red red green red yellow red green red red green red red/ green green red red/ green green red red
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 47 of 63 as mentioned above, pin led2 is deactivated in normal - standard status indication mode ( extended_sta- tus_indication = ?0? and dual_led_mode = ?0?) for downward compatibility. in this case, the green led shall be connected directly to pin uout or different sensor supply. 3.9.2. communication via addressing channel as soon as the addressing channel becomes activated for telegram communication (see chapter 3.3 addressing channel input ird on page 6), led1 is operated as addressing channel output port. this output mode takes precedence over any status indication at led1. if the dual_led_mode flag is set, led2 is switched inactive (high impedance) while the addressing channel is active. this is to avoid interference to the data communication by mixed optical signals. 3.9.3. master-, repeater-, monitor mode in master-, repeater- and monitor mode led1 provides the manchester-ii-coded, re-synchronized equivalent of the telegram signal received at the as-i input channel. the polarity of the manchester-ii-coded bit stream depends on the values of the pins di2 and di3. table 28: polarity of manchester-ii-signal at led1 input values at di2 and di3 are: description equal (?11?, ?00?) manchester-ii-signal is high active (default logic output value at no communication is ?0?). this mode is compatible to the a2si led output unequal (?01?, ?10?) manchester-ii-signal is low active (default logic output value at no communication is ?1?). note: the complemented definition was chosen to retain backward compatibility to a2si based as-i master designs. every received as-i telegram is checked for consistency with the protocol specifications and timing jitters become removed as long as they stay within the specified limits. in case a telegram error is detected, the output signal becomes disturbed in such a way that following logic can also recognize the man output signal being erroneous. led2 is always logic high (high impedance) in master-, repeater- and monitor mode to reduce internal power dissipation of the ic. in such applications, the green led shall be connected to pin uout or different supply levels. 3.10. oscillator pins osc1, osc2 table 29: oscillator pin parameters symbol parameter min typ. max unit note v osc_in input voltage range -0.3 v u5r v c osc external parasitic capacitor at oscillator pins osc1, osc2 0 8 pf c load dedicated load capacity 12 pf v il input ?low? voltage 0 1.5 v 1 v ih input ?high? voltage 3.5 v u5r v 1 1 for external clock applied to osc1
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 48 of 63 3.11. ic reset any ic reset turns the data output and parameter output registers to 0xf and forces the corresponding output drivers to high impedance state. except at power on reset, data strobe and parameter strobe signals are simultaneously generated to visualize possibly changed output data to external circuitry. the data_exchange_disable flag becomes set during ic reset, prohibiting any data port activity right after ic initialization and as long as the external circuitry was not pre-conditioned by decent parameter output data. consequently the as-i master has to send a write_parameter call in advance of the first data_exchange request to an initialized slave. following ic initialization times apply: table 30: ic initialization times symbol parameter min max unit note t init initialization time after softwar e reset (generated by master calls reset_slave or broadcast_reset ) or external reset via dsr 2 ms 1 t init2 initialization time after power on 30 ms 2 t init3 initialization time after power on with high capacitive load 1000 ms 3 1 guaranteed by design 2 ?power on? starts latest at v uin = 18v, external capacitor at pin uout less than or equal 10f 3 c uout = 470f, t init3 is guaranteed by design only 3.11.1. power on reset in order to force the ic into a defined state after power up and to avoid uncontrolled switching of the digital logic if the 5v supply (u5r) breaks down below a certain minimum level, a power on reset is executed under the following conditions: table 31: power on reset threshold voltages symbol parameter min max unit note v por1f v u5r voltage to trigger internal reset procedure, falling voltage 1.2 1.7 v 1 v por1r v u5r voltage to trigger init procedure, rising voltage 3.5 4.3 v 1 t low power-on reset pulse width 4 6 s 1 guaranteed by design uin u5r t low reset about 15v v por1r v por1r figure 17: power-on behavior (all modes)
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 49 of 63 note: the power-on reset circuit has a threshold voltage reference. this reference matches the process tolerance of the logic levels and must not be very accurate. all values depend slightly on the raise and fall time of the supply voltage. 3.11.2. logic controlled reset the ic also becomes reset after reception of reset_slave or broadcast_reset commands, expiration of the (enabled) communication watchdog or entering of a fo rbidden state machine state (i.e. due to heavy emi). note: in case the addressing channel is activated and the ac current input mode is selected, reset_slave and broadcast_reset calls are processed differently than in normal operation! see corresponding explanations in chapter 3.3 addressing channel input ird on page 6. 3.11.3. external reset the ic can be reset externally by pulling the dsr pin low for more than a minimum reset time. the external reset input function is provided in every operational mode of the ic ? slave mode, master mode, repeater mode and monitor mode . the following signal timings apply: table 32: timing of external reset symbol parameter min max unit note t noreset dsr low time for no reset initiation 35 s t reset reset execution time, dsr h/l transition to hi-z output drives at do0...do3, p0?p3 44 s t init state machine initialization time after reset (e2prom read out) 2 ms in contrast to the a2si, the external reset is gene rated ?edge sensitive? to the expiration of the t reset timer. the initialization procedure is starting immediately after t he event, independent of the state of dsr. a serious peripheral fault is recognized in slave mode if dsr still remains low after t reset + t init . the corresponding error state display is described in chapter 3.9 led outputs on page 6. dsr do0..do3 t noreset t reset t init hi-z po0..po3 hi-z data port output data parameter port output data serious peripheral fault figure 18 : timing diagram external reset via dsr
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 50 of 63 3.12. uart the uart performs a syntactical and timing wise analysis of the received telegrams at both telegram input channels (as-i input, addressing channel input), converts the pulse coded as-i input signal into a manchester-ii-coded bit stream and provides the receive register with decoded telegram bits. the uart also realizes the manchester-ii-coding of a slave answer (slave mode only) and controls the telegram data paths at the different operational modes of the ic (slave mode, master mode, repeater mode, monitor mode). in slave mode data communication takes place on the as-i input and as-i output ports (as-i receiver + as-i transmitter) by default. the addressing channel (ird input + led1 output) can be activated by a magic sequence sent to the ird input (see chapter 3.3 addressing channel input ird). if the addressing channel is activated, the as-i channel is turned inactive. re-activation of the as-i channel requires a reset of the ic. in master-, repeater- and monitor mode the output signal of the manchester coder (as-i pulse to man signal conversion) is resynchronized and forwarded to pin led1. any pulse timing jitters of the received as-i signal become removed, as long as they stay within the specif ied maximum limits. if the received as-i telegram does not pass one of the different error checks (see detailed description below), the led1 output is distorted in such a way that it will not form any as-i telegram signal anymore. in master-, repeater- and monitor mode the asi4u provides a simple interface function between as-i channel and addressing channel. the channel receiving an input signal first while the uart is in idle state (no active communication) is activated and locked until a co mmunication pause is detected on that channel. 3.12.1. as- i input channel the comparator stages at the as-i-line receiver generate two pulse-coded output signals ( p_pulse , n_pulse ) disjoining the positive and negative telegram pulses for further processing. to reduce uart sensitivity on erroneous spike pulses, pulse filters suppress any p_pulse , n_pulse activity of less than 750 ns width. after filtering, the p_pulse and n_pulse signals are checked in accordance with the as-i complete specification for following te legram transmission errors: start_bit_error the initial pulse following a pause must have negative polarity. violation of this rule is detected as start_bit_error . the first pulse is the reference for bit decoding. the first bit detected shall be of the value 0. alternating_error two consecutive pulses must have different polarity. violation of this rule is detected as alternating_error . note: a negative pulse shall be followed by a positive pulse and vice versa. timing_error within any master request or slave response, the digital pulses that are generated by the receiver are checked to start in periods of s s s n ? ? ? 500 . 1 875 . 0 ) 3 * ( ? ? after the start of the initial negative pulse, where n = 1 ... 26 for a master request and n = 1 ... 12 for a slave response. violation of this rule is detected as timing_error. note: there is a certain pulse timing jitter a ssociated with the receiver output signals (compared to the analog signal waveform) due to sampling and offset effects at the comparator stages. in order to take the jitter effects into account, the timing tolerance specifications differ slightly from the definitions of the as-i complete specification. no_information_error derived from the manchester-ii-coding rule, either a positive or negative pulse shall be detected in periods of s s s n ? ? ? 500 . 1 875 . 0 ) 6 * ( ? ? after the start of the initial negative pulse, where n = 1 ... 13 for a master request and n = 1 ... 6 for a slave response. violation of this rule is detected as no_information_error . note: the timing specification relates to the receiver comparator output signals. there is a certain pulse timing jitter in the digital output signals (compared to the analog signal waveform) due to sampling and offset effects at the comparator stages.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 51 of 63 in order to take the jitter effects into account, the timing tolerance specifications differ slightly from the definitions of the as-i complete specification. parity_error the sum of all information bits in master requests or slave responses (excluding start and end bits, including parity bit) must be even. violation of this rule is detected as parity_error. end_bit_error the pulse to be detected s s s n ? ? ? 500 . 1 875 . 0 ) 6 * ( ? ? after the start pulse shall be of positive polarity, where n = 13 (78 ? s) for a master request and n = 6 (36 ? s) for a slave response. violation of this rule shall be detected as an end_bit_error. note: this stop pulse shall finish a master request or slave response. length_error telegram length supervision is processed as follows. if during the first bit time after the end pulse of a master request (equivalent to the 15 th bit time) for synchronized slaves (during the first three bit times for not synchronized slaves, equivalent to the bit times 15 to 17) or during the first bit time after the end pulse of a slave response (equivalent to the 8 th bit time) a signal different from a pause is detected, a length_error is detected. if at least one of these errors occurs, the received telegram is treated invalid. in this case, the uart will not generate a receive strobe signal, move to asynchronous state and wait for a pause at the as-i line input. after a pause was detected, the uart is ready to receive the next telegram. receive strobe signals are generally used to validate the correctness of the received data. in master- and monitor mode the signals are visible at the parameter ports for further processing by external circuitry. corresponding parameter port configurations can be found at table 17 on page 6. in slave mode, a master receive strobe starts the internal processing of a master request. if the uart was in asynchronous state before the signal was generated, it changes to synchronous state thereafter. in case the received slave address matches the stored address of the ic, the transmitter is turned on by the receive strobe pulse, letting the output driver settles smoothly at the operation point.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 52 of 63 3.12.2. addressing channel the signal logic of the addressing channel follows the definition of a manchester-ii-coded as-i signal. the default state (inactive) is defined by a logic high value. depending on the input mode of the ird pin (voltage/current) a logic high is either represented by a voltage signal > 3.5v or an input current of i ird_offset + i ird_amplitude. a valid communication is started on a falling edge of the input signal (middle of start bit) and ended on a rising signal edge (middle of end bit) and followed by t he detection of a telegram pause. the information is represented by falling (=?0?) or rising (=?1?) signal transitions in the middle of every bit time (see figure 19) equivalent to the as-i input channel, the signals received at the addressing channel input (ird pin) are checked for telegram transmission errors. the checking, however, is only performed in slave mode. in master-, repeater- and monitor mode, the ird signal is ch ecked only for logical correctness. it is directly forwarded to the as-i line transmitter avoiding any additional logic delays. note: because the telegram checking is disabled on the addressing channel in master-, repeater- and monitor mode, corresponding receive strobe signals are neither displayed at the parameter ports nor generated for internal purposes. the master control logic must care to deliver correctly timed man-signals, ensuring that the resulting as-i telegrams fulfill the specified timing limits. following telegram transmission errors are detected in slave mode: start_bit_error the initial signal transition (after a pause) must be of falling edge. violation of this rule is detected as start_bit_error . no_information_error within a received telegram, signal transitions (of rising or falling edge) must occur in periods of s s s n ? ? ? 000 . 2 000 . 1 ) 6 * ( ? ? after the initial falling slope, where n = 1 ... 13. violation of this rule is detected as no_information_error . note: the addressing channel input (ird) only accepts master requests in slave mode. parity_error the sum of all information bits in master requests (excluding start and end bits, including parity bit) must be even. violation of this rule is detected as parity_error . end_bit_error the signal transition to be detected 13 * 6 ? s (78 ? s) after the initial falling start transition, shall be of rising slope. violation of this rule is detected as an end_bit_error . note: this stop transition shall finish the master request. length_error if during the first bit time after the end bit of a master request (equivalent to the 15 th bit time) for synchronized slaves (during the first three bit times for not synchronized slaves, equivalent to the bit times 15 to 17) a signal different from a pause is detected, a length_error is detected. figure 19: manchester-ii-modulation principle information bit stream transmitted man-ii-coded bit stream 0 0 1 0 1 pause
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 53 of 63 3.13. main state machine the state machine controls the overall behavior of the ic. depending on the configuration data stored in the e2prom, the state machine activates one of the different ic operational modes and controls the digital i/o ports accordingly. in slave mode it processes the re ceived master telegrams and computes the contents of the slave answer, if required. table 6 on page 6 lists all master calls that are decoded by the asi4u in slave mode. to prevent the critical situation in which the ic gets lo cked in a not allowed state (i.e. by imission of strong electromagnetic radiation) and thereby could jeopardize the entire system, all prohibited states of the state machine will lead to an unconditioned logic reset whic h is comparable to the as-i call ?reset slave (res)?. 3.14. communication monitor/watchdog the ic contains an independent communication monitor that observes the processing of data_exchange and write_parameter requests. if no such requests have been processed for more than 40.960ms (+5%) the communication monitor recognizes a no data/parameter exchange status and turns the red status led (led1) on. any following data_exchange or write_parameter request will let the communication monitor start over and turn the red status led off. the communication monitor is only activated at slav e addresses unequal to zero (0) and while the ic is processing the first write_parameter request after initialization. it becomes deactivated at any ic reset or after the reception of a delete_address request. if the watchdog_active flag (e2prom firmware area) is set or the p0_watchdog_activation flag is set and parameter port p0 is logic high, the communication monitor is switched to the so-called watchdog mode. if the communication monitor detects a no data/parameter exchange status in active watchdog mode, it immediately invokes an unconditioned ic reset, switching all data and parameter outputs inactive, generating corresponding data and parameter strobe signals, setting the data_exchange_disable flag and starting the ic initialization procedure. in order to resume to normal data port communication after a watchdog ic reset, the master has to send a write_parameter request again before data port communication can be reestablished. this ensures new parameter setup of possibly connected external circuitry. 3.15. toggle watchdog for 4i/4o processing in extended address mode as described in chapter 3.7.5 on page 6 a special 4i/4o data processing is supported in extended address mode. the transmission of a 4 bit wide output word is achieved by alternation of a high and a low nibble in consecutive transactions. to ensure that both output nibbles become refreshed continuously by the master, the alternation of the i2 bit in the data_exchange call can be supervised by an i2 toggle watchdog in the ic. the toggle watchdog is enabled at slave addresses unequal to zero (0) and while the ic is processing the first data output event after initialization. it becomes disabled at any ic reset or after the reception of a delete_address request. the toggle watchdog function becomes activated only if the ic is operated in 4i/4o mode (id_code = 0xa, ext_addr_4i/4o_mode = ?1?) and if either the watchdog_active flag is set in the e2prom or the p0_watchdog_activation flag (also e2prom) is set and parameter port p0 is logic high. if there is no alternation of bit i2 for 327ms (+16ms) at any time after the enable event, an activated toggle watchdog invokes an unconditioned ic reset, switching all data and parameter outputs inactive, generating corresponding data and parameter strobe signals, setting the data_exchange_disable flag and starting the ic initialization procedure. thus, the reaction of th e ic is the same as for an expired communication watchdog.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 54 of 63 3.16. write protection of id_code_extension_1 the id_code_extension_1 register can either be manufacturer configurable or user configurable. ? if the flag id_code1_protect is set (?1?) in the firmware area of the e2prom, id_code_extension1 is manufacturer configurable. in this case the slave response to a read_id_code_1 request is constructed out of the data stored in the protected_id_code_extension1 register in firmware area of the e2prom. it doesn?t matter which data is stored in the id_code_extension1 register in the user area. the ic will always respond with the protected manufacturer programmed value. there is one exception to this principle. if the ic is operated in extended address mode, bit3 of the returned slave response is taken from the id_code_extension1 register in the user area . this is because bit 3 functions as a/b slave selector bit in this case and must remain user configurable. to ensure consistency of id_code_extension1 stored in the data image of master as well as in the e2prom of the slave, the asi4u will not process a write_id_code1 request if the data sent does not match the data that is stored in protected part of the id_code_extension1 register. it will neither access the e2prom nor send a slave response in this case. note: as defined in the as-i complete specification a modification of the a/b slave selector bit must be performed bit selective. that means the as-i master must read the id_code_extension1 first, modify bit3 and send the new 4 bit word that consis ts of the modified bit3 and the unmodified bits 2 ? 0 back to the slave. ? if the id_code1_protect flag is not set (?0?), id_code_extension1 is completely user configurable. the data to construct the slave response to a read_id_code_1 request is completely taken from the id_code_extension1 register in the user area. in this configuration a write_id_code1 request will always be answered and initiate an e2prom write access procedure.
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 55 of 63 3.17. power supply the power supply block provides a sensor supply, which is inductively decoupled from the as-i bus voltage, at pin uout. the decoupling is realized by an electronic inductor circuit, which basically consists of a current source and a controlling low pass. the time constant of the low pass, that has influence to the resulting input impedance at pin uin, can be adjusted by an external capacitor at pin cap. the electronic inductor can be turned off if pin cap is connected to 0v. this shuts down the current source between uin and uout requiring an external connection between uin and uout for proper ic operation. the possibility to turn off the electronic inductor is helpful to realize high symmetrical extended power applications (i.e. as-i connected actuators with large load currents). overloading the electronic inductor for more than 2 seconds by drawing too much current shuts down the entire ic in order to avoid a deviation of the input impedance, which would have negative influence to the communication of the remaining as-i network clients. the fail-safe shutdown mode can only be left by power cycling the as-i supply voltage. a second function of the power supply block is to generate a regulated 5v supply for operation of the internal logic and some analog circuitry. the voltage is provided at pin u5r an can be used to supply external circuitry as well, as long as the current requirements stay within in the specified limits. see table 33 below. because the 5v supply is generated out of the decoupled sensor supply at uout, the current drawn at u5r has to be subtracted from the total available load current at uout. the power supply dissipates the major amount of power: ptot = v drop * i uout + (v uout -5v) * i 5v in total, the power dissipation shall not exce ed the specified values of chapter 1.1. to cope with fast internal and external load changes (spikes) external capacitors at uout and u5r are required. the 0v pin defines the ground reference voltage for both uout and u5r. 3.17.1. voltage output pins uout and u5r table 33: properties of voltage output pins uout and u5r symbol parameter min max unit note v uin positive supply voltage for ic operation 16 33.1 v 1 v drop voltage drop from pin uin to pin uout 5.5 2 6.7 2 v v uin > 22v v uout uout output supply voltage v uin - v dropmax v uin - v dropmin v i uoutmax v uoutp uout output voltage pulse deviation 1.5 v 2 t uoutp uout output voltage pulse deviation width 2 ms 2 v u5r 5v supply voltage 4.5 5.5 v i uout uout output supply current 0 55 2 ma i u5r = 0 2 i 5v u5r output supply current 0 4 ma i o total output current i uout + i 5v 55 ma i uouts short circuit output current 50 ma c buout blocking capacitance at uout 10 470 f c b5v blocking capacitance at u5r 1 f 1 parameter copied from table 2: operating conditions 2 c uout = 10f, output current switches from 0 to i uoutmax and vice versa
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 56 of 63 3.17.2. input impedance (as-i bus load) the following parameters are determined with short cut between the pins asip and uin and the pins asin and 0v, respectively. table 34: as-i bus load properties symbol parameter min max unit note r in1 equivalent resistor of the ic 13,5 k ? 1,2 l in1 equivalent inductor of the ic 13,5 mh 1,2 c in1 equivalent capacitor of the ic 30 pf 1,2 r in2 equivalent resistor of the ic 13,5 k ? 1,2 l in2 equivalent inductor of the ic 12 13,5 mh 1,2 c in2 equivalent capacitor of the ic 15 + (l-12mh)*10pf/mh pf 1,2 c zener parasitic capacitance of the external over-voltage protection diode (zener diode) 20 pf 1 1 the equivalent circuit of a slave, which is calculated from the impedance of the ic and the paralleled external over-voltage protection diode (zener diode), has to satisfy the requirements of the as-i complete specification for extended address mode slaves. 2 subtracting the maximum parasitic capacitance of the external over voltage protection diode (20pf) either the triple r in1 , l in1 and c in1 or the triple r in2 , l in2 and c in2 has to be reached by the ic to fulfill the as-i complete specification. table 35: cap pin parameters symbol parameter min typ max unit note v cap_in input voltage range -0.3 v u5r v c cap external decoupling capacitor 47 nf note: in some application a serial to c cap connected resistor may enhance the impedance behavior of the internal electronic inductor. depending of the application this resistor has to be dimensioned between 10 ? 100 ? . the decoupling capacitor defines an internal low-pass filter time constant; lower values decrease the impedance but improve the turn-on time. higher values do not improve the impedance but do increase the turn-on time. the turn-on time also depends on the load capacitor at uout. after connecting the slave to the power the capacitor is charged with the maximum current i uout . the impedance will increase when the voltage allows the analog circuitry to fully operate. 3.18. thermal and overload protection the ic continuously observes its silicon die temperature. if the temperature rises above around 140c for more than 2 seconds the ic will be put into shutdown and stay there until the next power-on reset occurs. the circuit also becomes shut down if u out is overloaded (e.g. shorted to gnd) for more than 2 seconds. table 36: shutdown temperature symbol parameter min max unit note t shut chip temperature for over temperature shut down 125 160 c
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 57 of 63 4 application circuits the following figures show typical application cases of the asi4u. please note that these schematics show only principle circuit drafts. for more detailed application information see the separate asi4u application notes document. figure 20 outlines a standard slave application circuit compliant to the first as-i ic. figure 21 shows an extended power application circuit with externally decoupled sensor supply. a master mode application is shown in figure 22. green standard application with bi-directional data i/o uo ut a sin osc1 osc2 cap a sip uin u5r fid 0v remark: depending on i/o-configuration, do- and di-ports are connected and multiplex-flag is set asi+ asi- +24v dio-0 dio-1 dio-2 dio-3 dsr&reset p0 p1 p2 p3 ps led2 led1 asi4u zmm 39 1n4001 8/16mhz 47n 100n 1 0 10 n figure 20: standard application circ uit with bi-directional data i/o
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 58 of 63 ext ended pow er application with ir-addressing option led2 led1 green asi4u zmm 39 2 x zm m 4, 7 2 x zmm 4,7 1n4001 1n4148 8/16mhz 8mh 8mh 1 100n 10 10n figure 21: extended power application circuit
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 59 of 63 figure 22: asi4u master mode application master/repeater application led 2 led1 fid asi4u 8/16 mhz 1 n4001 zmm 39 47n 1 0 10n
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 60 of 63 5 package outline (sop28 / asi4u-e) the ic is packaged in a 28 pin sop-package (figure 23) that has the dimensions as shown in figure 24 and table 37. figure 23: sop package figure 24: package dimensions table 37: package dimensions (mm) symbol a a1 b c e d e l h h ? nominal 1,27 0,25 x 45 maximum 2,35 0,10 0,33 0,23 17,70 7,40 0,41 10,01 0 minimum 2,65 0,30 0,51 0,32 18,10 7,60 1,27 10,64 8
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 61 of 63 6 package outline (ssop2 8 / asi4u / asi4u-f) the ic is packaged in a 28 pin ssop-package (figure 25) that has the dimensions as shown in figure 26 and table 38. table 38: package dimensions (mm) symbol a a1 a2 b c d e e h l ? nominal 1.86 0.13 1.73 0.30 0.15 10.20 5.30 7.80 0.75 4 maximum 1.99 0.21 1.78 0.38 0.20 10.33 5.38 7.90 0.95 8 minimum 1.73 0.05 1.68 0.25 0.13 10.07 5.20 0.65 bsc 7.65 0.55 0 figure 25: ssop package figure 26: package outline dimensions
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 62 of 63 7 package marking top marking: asi4u or asi4u-e or asi4u-f product name zmdi manufacturer r- revision code yyww date code (year and week) l assembly location zz traceability code g1 ?green? rohs-compliant package bottom marking: llllll zmdi lot number for ics pre-programmed to master mode the string ?-m? follows the product name. for ics capable for an operation temperature up to 105c the string ?-e? follows the product name. for ics capable for an operation temperature up to -40c the string ?-f? follows the product name. pin 1 top view bottom vie w pin 1 llllll a si4u zmdi r-yywwlzz g1 + figure 27: package marking
asi4u / asi4u-e / asi4u-f spec. 3.0 compliant universal as-i ic data sheet april 2, 2012 ? 2012 zentrum mikroelektronik dresden ag ? rev. 2.2 all rights reserved. the material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. the information furnished in this publication is subject to changes without notice. 63 of 63 8 ordering information ordering code type operating temperature range package type rohs conform packaging minumum order quantity asi4ue-g1-st standard -25c to +85c ssop28 / 5.3mm y tube (47 parts/tube) 470 pcs. (10 tubes) asi4ue-g1-sr standard -25c to +85c ssop28 / 5.3mm y tape & reel (1500 parts/reel) 1500 pcs. (one reel) asi4ue-g1-sr-7 standard -25c to +85c ssop28 / 5.3mm y tape & reel (500 parts/reel) 500 pcs. (one 7" reel) asi4ue-g1-mt master -25c to +85c ssop28 / 5.3mm y tube (47 parts/tube) 470 pcs. (10 tubes) asi4ue-g1-mr master -25c to +85c ssop28 / 5.3mm y tape & reel (1500 parts/reel) 1500 pcs. (one reel) asi4ue-e-g1-st standard -25c to +105c sop28 / 300 mil y tube (27 parts/tube) 270 pcs. (10 tubes) asi4ue-e-g1-sr standard -25c to +105c sop28 / 300 mil y tape & reel (1000 parts/reel) 1000 pcs. (one reel) asi4ue-f-g1-st standard -40c to +85c ssop28 / 5.3mm y tube (47 parts/tube) 470 pcs. (10 tubes) ASI4UE-F-G1-SR standard -40c to +85c ssop28 / 5.3mm y tape & reel (1500 parts/reel) 1500 pcs. (one reel) 9 related documents ? as-i family ordering guide ? asi4u feature sheet ? asi4u errata sheet ? asi4u safety advice ? asi4u release note 10 related products ? a2si universal as-interface ic ? a2si-lite low-cost as-interface ic ? sap5 universal as-interface ic sales and further information www.zmdi.com asi@zmdi.com zentrum mikroelektronik dresden ag grenzstrasse 28 01109 dresden germany zmd america, inc. 1525 mccarthy blvd., #212 milpitas, ca 95035-7453 usa zentrum mikroelektronik dresden ag, japan office 2nd floor, shinbashi tokyu bldg. 4-21-3, shinbashi, minato-ku tokyo, 105-0004 japan zmd far east, ltd. 3f, no. 51, sec. 2, keelung road 11052 taipei taiwan zentrum mikroelektronik dresden ag, korean office posco centre building west tower, 11th floor 892 daechi, 4-dong, kangnam-gu seoul, 135-777 korea phone +49.351.8822.7274 fax +49.351.8822.87274 phone +855-ask-zmdi (+855.275.9634) phone +81.3.6895.7410 fax +81.3.6895.7301 phone +886.2.2377.8189 fax +886.2.2377.8199 phone +82.2.559.0660 fax +82.2.559.0700 disclaimer : this information applies to a product under development. its characteristics and specifications are subject to change without notice. zentrum mikroelektronik dresden ag (zmd ag) assumes no obligation regarding future manufacture unless otherwise agreed to in writing. the information furnished he reby is believed to be true and accurate. however, under no circumstances shall zmd ag be liable to any customer, licensee, or any other third party for any special, indirect, in cidental, or consequential damages of any kind or nature whatsoever arising out of or in any way related to the furnishing, performance, or use of this technical data. zmd ag hereby ex pressly disclaims any liability of zmd ag to any customer, licensee or any other third party, and any such customer, licensee and any other third party hereby waives any liability of zmd ag for any damages in connection with or arising out of the furnishing, performance or use of this technical data, whether based on contract, warranty, tort (including negligence), st rict liability, or otherwise.
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